MODE

XLAT

SIN(a)

SCLK

SOUT(b)

BLANK

GSCLK

OUT0

(current)

OUT1

(current)

OUT15

(current)

XERR

1

192X2

DCb

MSB

DCa

LSB

DCb

MSB

1

384

385

1

384

385

1

1

4096

1

GSb1

MSB

GSa1

LSB

GSb1

MSB

GSb2

MSB

GSa2

LSB

GSb2

MSB

SIDb2

MSB

SIDb2

MSB-1

SIDb1

MSB

SIDb1

MSB-1

SIDa1

LSB

GSb3

MSB

-

-

-

192

96X2

TLC59401

www.ti.com

SBVS137 – DECEMBER 2009

Figure 14. Timing Chart for Two Cascaded TLC59401 Devices

ERROR INFORMATION OUTPUT

The open-drain output XERR is used to report both of the TLC59401 error flags, TEF and LOD. During normal

operation, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is pulled up to

VCC through an external pull-up resistor. If TEF or LOD is detected, the internal transistor is turned on, and XERR

is pulled to GND. Because XERR is an open-drain output, multiple ICs can be ORed together and pulled up to

VCC with a single pull-up resistor. This capability reduces the number of signals needed to report a system error

(see Figure 22).

To differentiate the LOD and TEF signal from the XERR pin, LOD can be masked out with BLANK pulled high.

Table 2. XERR Truth Table

ERROR CONDITION

ERROR INFORMATION

SIGNALS

TEMPERATURE

OUTn VOLTAGE

TEF

LOD

BLANK

XERR

TJ < T(TEF)

Don't care

Low

X

High

High

TJ > T(TEF)

Don't care

High

X

Low

OUTn > V(LED)

Low

Low

High

TJ < T(TEF)

OUTn < V(LED)

Low

High

Low

Low

OUTn > V(LED)

High

Low

Low

TJ > T(TEF)

OUTn < V(LED)

High

High

Low

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