TSA1203

Application information

19/30

8.5

Power consumption optimization

The internal architecture of the TSA1203 makes it possible to optimize power consumption

according to the sampling frequency of the application. For this purpose, an external resistor

is placed between IPOL and the analog ground pins. Therefore, the total dissipation can be

optimized over the full sampling range (0.5 Msps to 40 Msps).

The TSA1203 combines the highest performance with the lowest consumption at 40 Msps

when Rpol is equal to 18 kΩ. This value is nevertheless dependent on the application and the

environment.

In the lower sampling frequency range, this value of resistor may be adjusted in order to

decrease the analog current without any degradation of dynamic performance.

Table 12 gives some values to illustrate this.

8.6

Layout precautions

To use the ADC circuits most efficiently at high frequencies, some precautions have to be

taken for power supplies:

●

The implementation of 4 proper separate supplies and ground planes (analog, digital,

internal and external buffer ones) on the PCB is mandatory for high speed circuit

applications to provide low inductance and low resistance common return.

The separation of the analog signal from the digital output part is essential to prevent

noise from coupling onto the input signal. The best compromise is to connect AGND,

DGND, GNDBI in a common point whereas GNDBE must be isolated. Similarly, the

AVCC, DVCC and VCCBI power supplies must be separate from the VCCBE power

supply.

●

Power supply bypass capacitors must be placed as close as possible to the IC pins in

order to improve high frequency bypassing and reduce harmonic distortion.

●

All inputs and outputs must be properly terminated with output termination resistors;

thus, the amplifier load is resistive only and the stability of the amplifier is improved. All

leads must be wide and as short as possible especially for the analog input in order to

decrease parasitic capacitance and inductance.

●

To keep the capacitive loading as low as possible at digital outputs, short lead lengths

of routing are essential to minimize currents when the output changes. To minimize this

output capacitance, use buffers or latches close to the output pins.

●

Choose component sizes as small as possible (SMD).

Table 12.

Total power consumption optimization depending on Rpol value

FS (Msps)

30

35

40

Rpol (kΩ)

38

28

18

Optimized power (mW)

145

180

215

Obsolete

Product(s)

- Obsolete

Product(s)