TMS320F28023DAS.B datasheet(85/147 Pages) TI2

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9.9.3 Serial Peripheral Interface (SPI) Module

The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available.

The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to

16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for

communications between the MCU and external peripherals or another processor. Typical applications include

external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.

Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

• Four external pins:

– SPISOMI: SPI slave-output/master-input pin

– SPISIMO: SPI slave-input/master-output pin

– SPISTE: SPI slave transmit-enable pin

– SPICLK: SPI serial-clock pin

Note

All four pins can be used as GPIO if the SPI module is not used.

• Two operational modes: master and slave

Baud rate: 125 different programmable rates.

(SPIBRR

LSPCLK

rate

Baud

127

SPIBRR

when

LSPCLK

rate

Baud

SPIBRR

when

• Data word length: 1 to 16 data bits

• Four clocking schemes (controlled by clock polarity and clock phase bits) include:

– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling

edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising

edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

• Simultaneous receive and transmit operation (transmit function can be disabled in software)

• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.

• Nine SPI module control registers: In control register frame beginning at address 7040h.

Note

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a

as zeros. Writing to the upper byte has no effect.

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SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021

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TMS320F28023DAS.B Datasheet(PDF) 85 Page - Texas Instruments

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