Ω,

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

Propagation Delay Time

Clock to Q

5

200

400

ns

10

80

160

15

60

120

Propagation Delay Time

5

225

450

ns

10

95

190

15

70

140

Propagation Delay Time

5

125

250

ns

10

55

110

15

40

80

Setup Time

Data to Clock

5

240

120

ns

10

90

45

15

60

30

Setup Time

Load to Clock

5

240

120

ns

10

90

45

15

60

30

Setup Time

PE or TE to Clock

5

340

170

ns

10

140

70

15

100

50

Hold Time

5

0

ns

10

0

15

0

Transition Time

5

100

200

ns

10

50

100

15

40

80

CLock Input Pulse Width

5

170

85

ns

10

70

35

15

50

25

Maximum Clock Input Frequency

5

2

3

MHz

10

5.5

8.5

15

8

12

Clock Input Rise or Fall Time *

200

ns

70

15

Propagation Delay Time (40160B, 40161B)

Clear to Q

5

250

500

ns

10

110

220

15

80

160

Setup Time (40162B, 40163B)

Clear to Clock

5

340

170

ns

10

140

70

15

100

50

Hold Time (40162B, 40163B)

Clear to Clock

50

ns

10

0

15

0

Clear Removal Time (40162B, 40163B)

5

200

100

ns

10

100

50

15

70

35

Clear Input Pulse Width Low Level (40160B,

40161B)

5

170

85

ns

10

70

35

15

50

25

* If more than one unit is cascated in the parallel clocked application, tr should be made less than or equal to the sum of the fixed propagation delay

at 50 pF and the transition time of the carry output driving stage for the estimated capacitance

HCC/HCF40160B-40161B-40162-40163

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