Copyright © 2016

Microsemi

Page 4

Rev. 1.4, July 2017

CPG

– PoE BU

One Enterprise Aliso Viejo, CA 92656 USA

PD70211

PD Controller with Switching Regulator for

AF/AT/UPOE/HDBaseT/4-pair PoE Applications

Pin

Number

Designator

Description

12

ENABLE

A logic-level input to enable the converter. We can pull it constantly up, say with a 100k

resistor to VDD, to forcibly enable the converter. Provided the input supply has exceeded

any applicable UVLO thresholds, of course, as set on the VINS pin or on the VCC pin.

Internally, the ENABLE pin actually goes to the input of an OR-gate, the other input terminal

of which is tied to “POK” – a signal provided by the front-end. If the ENABLE pin is forced

high, the output of the OR-gate goes high and the converter is allowed to start (provided all

UVLO’s are past of course). If the ENABLE pin is held low, the internal node “POK” goes

active high when the PD’s front end conducts (power OK), so the OR-gate goes high once

again. In this case the switching converter turns ON naturally and correctly as required by

the PoE standard. However, for supporting wall-adapters, injecting power after the front-

end (at the input of the converter), we can forcefully turn the converter ON without the

front-end signaling “PGOOD”, by not tying the ENABLE pin low, but by tying it high (to VDD).

That will turn ON the converter irrespective of the state of the front-end (conducting or

not), and whether there is any incoming PoE power or not.

13

VINS

The VINS pin is a programmable UVLO pin. The converter will turn ON provided the voltage

on the VINS pin is above 1.2V (and VCC is not in UVLO, and ENABLE pin is also high –

connected to VDD for example). The converter will stop switching (turn OFF) when the

voltage on the VINS pin falls below 1.2V (or if ENABLE is taken low, or if VCC falls outside its

operating range). Thus by connecting a voltage divider between input rail and IC ground, we

can set the UVLO threshold to enable switching. However, to have a smooth startup, it is

advisable to have some hysteresis too, by means of a resistor between VINS and HYST as

explained below.

14

HYST

This is the output of the UVLO comparator as shown in the Block Diagram. We connect a

“hysteresis resistor” from HYST pin to VINS pin to create positive feedback (and hysteresis).

Initially, as the input voltage is rising, the VINS pin voltage is below 1.2V and so the output of

the UVLO comparator is low, and the hysteresis resistor falls in parallel to the lower resistor

of the UVLO divider placed at the VINS pin, assisting it by pulling down the VINS pin voltage

further. As soon as the rising UVLO threshold is exceeded (VINS > 1.2V), the output of the

UVLO comparator suddenly goes high (up to VDD) and the hysteresis resistor, effectively

comes partially across the upper resistor of the UVLO divider, assisting it in the act of pulling

up on the VINS pin. This feedback therefore increases the voltage on the VINS pin. And so,

now the input rail has to fall to a much lower level to allow the VINS pin voltage to fall below

1.2V. That is how hysteresis is created by positive feedback action through the hysteresis

resistor. The exact math is in the applications information of this datasheet. Note that HYST

pin always toggles high or low depending on whether the voltage on the VINS pin is above

or below 1.2V respectively. This can always be used to simultaneously drive an opto, to

indicate when the input rail is above the programmed rising threshold and when it falls

below the programmed falling threshold.

15

SYNC

Used to synchronize the LX7309 to a frequency higher than its default value as set on RFREQ

pin. The synchronizing clock must be 2x the desired sync frequency, with a maximum

synchronizing clock frequency of 1MHz (for 500kHz PWM frequency). The PG pin’s rising

edge will occur at the same instant as the rising edge of the clock being applied on the SYNC

pin.