TH8082KDC datasheet(18/26 Pages) MELEXIS

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TH8082

Enhanced SoloLIN Transceiver

TH8082 – Datasheet

Page 18 of 26

3901008082

Feb 2007

Rev 007

5.3

Duty Cycle Calculation

TxD

BUS

RxD

VSUP

58.1%

28.4%

100%

74.4%

42.2%

tdom(max)

tdom(min)

trec(min)

trec(max)

VSS

58.1%

28.4%

tBit

Figure 9 - Duty cycle calculation in accordance to LIN 2.0

With the timing parameters shown in Figure 9 two duty cycles , based on trec(min) and trec(max) can be

calculated as follows :

D1 = trec(min) / (2 * tBit)

D2 = trec(max) / (2 * tBit)

For proper operation at 20KBit/s ( tBit = 50µs) the LIN driver has to fulfil the duty cycles specified in chapter

2.4 Dynamic Characteristics for supply voltages of 7 to 18V and the defined standard loads .

Due to this simplified definition there is no need to measure slew rates, slope times, transmitter delays and

dominant voltage levels as specified in the LIN physical layer specification 1.3.

The device within the D1/D2 duty cycle range operates also in applications with reduced bus speed of

10.4KBit/s or below.

In order to minimize EME, the slew rates of the transmitter can be reduced (approximately by 2 times). Such

devices have to fulfil the duty cycle definition D3/D4 in the LIN physical layer specification 2.0. Devices within

this duty cycle range cannot operate in 20KBit/s applications.

TH8082KDC Datasheet(PDF) 18 Page - Melexis Microelectronic Systems