Rev 1.0, May 21, 2007

Page 7 of 11

SL23EP05

Symbol

Description

Condition

Min

Typ

Max

Unit

tPLLOCK

PLL Lock Time[9]

From 90% of VDD to valid clocks presented on

all output clock pins

––

1.0

ms

3.3V supply, >66 MHz, <15 pF

–20

50

ps

3.3V supply, >66 MHz, <30 pF, standard drive

–

40

100

ps

3.3V supply, >66 MHz, <30 pF, high drive

–

40

100

ps

2.5V supply, >66 MHz, <15 pF, standard drive

–

35

90

ps

2.5V supply, >66 MHz, <15 pF, high drive

–

30

60

ps

CCJ

[2,3]

Cycle-to-cycle Jitter

2.5V supply, >66 MHz, <30 pF, high drive

–

50

125

ps

3.3V supply, 66–100 MHz, <15 pF

–

18

50

ps

3.3V supply, >100 MHz, <15 pF

–

15

35

ps

3.3V supply, >66 MHz, <30 pF, standard drive

–

30

75

ps

3.3V supply, >66 MHz, <30 pF, high drive

–

25

60

ps

2.5V supply, >66 MHz, <15 pF, standard drive

–

25

60

ps

2.5V supply, 66–100 MHz, <15 pF, high drive

–

20

60

ps

PPJ

[2,3]

Peak Period Jitter

2.5V supply, >100 MHz, <15 pF, high drive

20

–45

ps

Notes:

3. Typical jitter is measured at 3.3V or 2.5V, 30 C with all outputs driven into the maximum specified load.