Rev 1.1, February 2, 2007

Page 4 of 13

SL23EP09

S2

S1

Clock A1-A4

Clock B1-4

CLKOUT

Output Source

PLL Status

0

0

Tri-state

Tri-state

Driven

PLL

On

0

1

Driven

Tri-state

Driven

PLL

On

1

0

Driven

Driven

Driven

Reference

Off

1

1

Driven

Driven

Driven

PLL

On

Table 2. Select Input Decoding

Figure 1. CLKIN Input to CLK A and B Delay

(In terms of load difference between CLKOUT and CLK A and B)