CLC030 datasheet(12/29 Pages) NSC

12 / 29 page

Device Operation (Continued)

Writing of ancillary data to the FIFO, packet handling and

insertion into the video data stream are controlled by a

system of masking and control bits in the control registers.

These and other ancillary data control functions such as

CHKSUM ATTACH IN are explained in detail later in this

data sheet.

MULTI-FUNCTION I/O PORT

The Multi-function I/O port can be configured to provide

immediate access to many control and indicator functions

within the CLC030 configuration and control registers. The

individual pins comprising this port may be assigned as input

or output for selected bits in the control data registers. The

multi-function I/O port is configured by way of an 8x6-bit

The pin configuration registers contain codes which assign a

control register bit to a particular I/O pin. Controls and indi-

cators that are accessible by the port and their correspond-

ing selection addresses are given in the I/O Pin Configura-

tion Register Addresses, Table 6. Table 2 gives the control

Caution: When writing data into the control registers via the

multi-function I/O port, ACLK must be toggled to register the

data as shown in Figure 4. It is not necessary to toggle

ACLK when reading data from the multi-function I/O port.

Example: Program multi-function I/O port bit-0 as the CRC

Luma Error bit output.

Set ANC/CTRL to a logic-low.

Set RD/WR to a logic-low.

Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG

Toggle ACLK.

Present 310h to AD[9:0] as the register data.

Toggle ACLK.

EDH/CRC SYSTEM

The CLC030 has EDH and CRC character generation and

insertion circuitry. The EDH system functions as described

in SMPTE Recommended Practice RP-165. The CRC sys-

tem functions as specified in SMPTE 292M. The EDH/CRC

polynomial generators accept parallel data from the input

insertion in the serial data. Incoming parallel data is checked

for errors and the EDH flags are updated automatically. EDH

check words and status flags for SDTV data are generated

using the polynomial X

16 +X12 +X6 + 1 per SMPTE RP165.

EDH check words are inserted in the serial data stream at

the correct positions in the ancillary data space and format-

ted per SMPTE 291M. Generation and automatic insertion of

the EDH check words is controlled by EDH Force and EDH

Enable bits in the control registers. After a reset, the initial

state of all EDH and CRC check characters is 00h.

The SMPTE 292M high definition video standard employs

CRC (cyclic redundancy check codes) error checking in-

stead of EDH. The CRC consists of two 18-bit words gener-

ated using the polynomial X

18 +X5 +X4 + 1 per SMPTE

292M. One CRC is used for luminance and one for chromi-

nance data. CRC data is inserted at the required place in the

video data according to SMPTE 292M. The CRCs appear in

the data stream following the EAV and line number charac-

ters.

EDH and CRC errors are reported in the EDH0, EDH1, and

EDH2 register sets of the configuration and control registers.

PHASE-LOCKED LOOP SYSTEM

The phase-locked loop (PLL) system generates the output

serial data clock at 10x (standard definition) or 20x (high

definition) the parallel data clock frequency. This system

consists of a VCO, dividers, phase-frequency detector and

internal loop filter. The VCO free-running frequency is inter-

nally set. The parallel data clock V

CLK is the reference for the

PLL. The PLL automatically generates the appropriate fre-

quency for the serial clock rate. Loop filtering is internal to

the CLC030. The VCO has separate analog and digital

power supply feeds: V

DDPLLA pin 62, VSSPLLA pin 61, VD-

DPLLD

pin 1, and V

SSPLLD pin 2. These may be separately

20000311

FIGURE 3. Ancillary Data Write Timing

20000312

FIGURE 4. I/O Port Data Write Timing

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