32-Macrocell MAX® EPLD
fax id: 6101
CY7C344
CY7C344B
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
January 1990 – Revised October 1995
1CY 7C34 4B
Features
• High-performance, high-density replacement for TTL,
74HC, and custom logic
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• 0.8-micron double-metal CMOS EPROM technology
(CY7C344)
• Advanced 0.65-micron CMOS EPROM technology to
increase performance (CY7C344B)
• 28-pin 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
package
Functional Description
Available in a 28-pin 300-mil DIP or windowed J-leaded ce-
ramic chip carrier (HLCC), the CY7C344/CY7C344B repre-
sents the densest EPLD of this size. Eight dedicated inputs
and 16 bidirectional I/O pins communicate to one logic array
block. In the CY7C344 LAB there are 32 macrocells and 64
expander product terms. When an I/O macrocell is used as an
input, two expanders are used to create an input path. Even if
all of the I/O pins are driven by macrocell registers, there are
still 16 “buried” registers available. All inputs, macrocells, and
I/O pins are interconnected within the LAB.
The speed and density of the CY7C344/CY7C344B makes it
a natural for all types of applications. With just this one device,
the designer can implement complex state machines, regis-
tered logic, and combinatorial “glue” logic, without using mul-
tiple
chips.
This
architectural
flexibility
allows
the
CY7C344/CY7C344B to replace multichip TTL solutions,
whether they are synchronous, asynchronous, combinatorial,
or all three.
Selection Guide
7C344B–10
7C344B–12
7C344–15
7C344B–15
7C344–20
7C344B–20
7C344–25
7C344B–25
Maximum Access Time (ns)
10
12
15
20
25
Maximum
Operating
Current (mA)
Commercial
200
200
200
200
200
Military
220
220
220
Industrial
220
220
220
220
Maximum Standby
Current (mA)
Commercial
150
150
150
150
150
Military
170
170
170
Industrial
170
170
170
170
Shaded area contains preliminary information.
Note:
1.
Numbers in () refer to J-leaded packages.
C344–1
Logic Block Diagram
MACROCELL 2
MACROCELL 4
MACROCELL 6
MACROCELL 8
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 16
MACROCELL 18
MACROCELL 20
MACROCELL 22
MACROCELL 24
MACROCELL 26
MACROCELL 28
MACROCELL 30
MACROCELL 32
MACROCELL 1
MACROCELL 3
MACROCELL 5
MACROCELL 7
MACROCELL 9
MACROCELL 11
MACROCELL 13
MACROCELL 15
MACROCELL 17
MACROCELL 19
MACROCELL 21
MACROCELL 23
MACROCELL 25
MACROCELL 27
MACROCELL 29
MACROCELL 31
G
L
O
B
A
L
B
U
S
I
O
C
O
N
T
R
O
L
INPUT
INPUT
INPUT
INPUT
15(22)
15(23)
27(6)
28(7)
INPUT
1(8)
INPUT/CLK 2(9)
INPUT
13(20)
INPUT
14(21)
I/O
3(10)
I/O
4(11)
I/O
5(12)
I/O
6(13)
I/O
9(16)
I/O
10(17)
I/O
11(18)
I/O
12(19)
I/O
17(24)
I/O
18(25)
I/O
19(26)
I/O
20(27)
I/O
23(2)
I/O
24(3)
I/O
25(4)
I/O
26(5)
64 EXPANDER PRODUCT TERM ARRAY
32
Pin Configurations
Top View
HLCC
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12 13 14 1516 1718
432
28 27 26
I/O
I/O
INPUT
INPUT
INPUT
I/O
I/O
INPUT
INPUT
INPUT/CLK
I/O
I/O
1
INPUT
C344–2
INPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT
INPUT
Top View
CerDIP
INPUT/CLK
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
C344–3
[1]
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