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INTEL386SX Datasheet(PDF) 53 Page - Intel Corporation |
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INTEL386SX Datasheet(HTML) 53 Page - Intel Corporation |
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53 / 102 page ![]() Intel386TM SX MICROPROCESSOR The complete bus state transition diagram including operation with pipelined address is given by Figure 512 Note it is a superset of the diagram for non- pipelined address only and the three additional bus states for pipelined address are drawn in bold The fastest bus cycle with pipelined address con- sists of just two bus states T1P and T2P (recall for non-pipelined address it is T1 and T2) T1P is the first bus state of a pipelined cycle 240187 – 26 Figure 511 Details of Address Pipelining During Cycles with Wait States 53 |
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