TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
INTRODUCTION
Preliminary
1-17
Signal Name
Shared Signal
Ball
Type Description – TCC763/ TCC764
BCLK
GPIO_B[21] / BM[0]
J9
I/O
I2S Bit Clock / GPIO_B[21] / Boot Mode Bit 0.
Internal pull-down resistor is active at power up.
LRCK
GPIO_B[22] / BM[1]
L11
I/O
I2S Word Clock / GPIO_B[22] / Boot Mode Bit 1
Internal pull-down resistor is active at power up.
MCLK
GPIO_B[23]
K12
I/O
I2S System Clock / GPIO_B[23]
DAO
GPIO_B[24] / BM[2]
K11
I/O
I2S Digital Audio data Output / GPIO_B[24] / Boot Mode
Bit 2
DAI
GPIO_B[25]
K10
I/O
I2S Digital Audio data Input / GPIO_B[25]
ADCDAT
H10
O
I2S Digital Audio data Output of audio CODEC(ADC).
Must be connected externally to GPIO_B25 (DAI)
LCH_OUT
E11
AO
DAC Left Channel Output of audio CODEC
RCH_OUT
E12
AO
DAC Right Channel Output of audio CODEC
LOUT
B9
AO
DAC Left Channel Line Output of audio CODEC
ROUT
A8
AO
DAC Right Channel Line Output of audio CODEC
RCH_IN
F1
AI
ADC Right Channel Input of audio CODEC
MIC_IN
A4
AI
Microphone Input of audio CODEC
LCH_IN
F2
AI
ADC Left Channel Input of internal audio CODEC
VMID
B5
AO
Mid-rail reference decoupling point
MICBIAS
D5
AO
Microphone Bias
WMODE
CSB
F3
I
CODEC I/F Control. Pull-down for normal operation.
Internal pull-up resistor is active at power up.
SDIN
GPIO_A[8] / BW[0]
D6
I/O
2-Wire MCU Data Input for CODEC
SCLK
GPIO_A[9] / BW[1]
E7
I/O
2-Wire MCU Clock Input for CODEC
CD DSP Interface Pins
CBCLK
GPIO_A[1]
D9
I/O
CD Data Bit Clock Input / GPIO_A[1]
CLRCK
GPIO_A[2]
E9
I/O
CD Data Word Clock Input / GPIO_A[2]
CDAI
GPIO_A[3]
E8
I/O
CD Data Input / GPIO_A[3]
External Interrupt Pins
EXINT[3]
GPIO_A15
A2
I/O
External Interrupt Request [3] / GPIO_A[15]
EXINT[2:0]
GPIO_A14 / FGPIO[14]
GPIO_A13 / FGPIO[13]
GPIO_A12 / FGPIO[12]
D3
B3
C3
I/O
External Interrupt Request [2:0] / GPIO_A[14:12] / FGPIO[14:12]
General Purpose I/O Pins
GPIO_A[15]
EXINT[3]
A2
I/O
GPIO_A[15] / External Interrupt Request 3
GPIO_A[14:12]
EXINT[2:0] / FGPIO[14:12]
D3
B3
C3
I/O
GPIO_A[15:12] / External Interrupt 3 ~ 0 / Fast GPIO bits 14 ~ 12
GPIO_A[11]
GPIO_A[10]
GPIO_A[9] / BW[1]
GPIO_A[8] / BW[0]
SDI2 / FGPIO[11] / SCL
FRM2 / FGPIO[10] / SDA
SCK2 / FGPIO[9] / SCL
SDO2 / FGPIO[8] / SDA
E4
E6
E7
D6
I/O
GPIO_A[11:8] / Bus Width bits 1 ~ 0 / General Purpose Serial I/O 2
Fast GPIO bits 11 ~ 8 / I2C signals.
The status of BW[1:0] is latched at the rising edge of nRESET and
used to determine external bus width. Refer to section “MEMORY
CONTROLLER” for BW[1:0] description.
GPIO_A[9:8] is internally connected with audio CODEC signals.
Refer to Figure 1.3 for more information.
GPIO_A[7:4]
SDI1 / FGPIO[7]
FRM1 / FGPIO[6]
SCK1 / FGPIO[5]
SDO1 / FGPIO[4]
B6
C6
B7
B8
I/O
GPIO_A[7:4] / General Purpose Serial I/O 1 / Fast GPIO bits 7 ~ 4
GPIO_A[3:1]
SDI0 / CDAI / FGPIO[3]
FRM0 / CLRCK / FGPIO[2]
SCK0 / CBCLK / FGPIO[1]
E8
E9
D9
I/O
GPIO_A[3:1] / General Purpose Serial I/O 0 / CD Interface Signals /
Fast GPIO bits 3 ~ 1
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
