L9823

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APPLICATIONS INFORMATION

The typical application diagram for parallel Input SPI control is shown in Figure 4.

Figure 4. Typical Application Circuit Diagram for the L9823 Circuit.

For higher current driving capability more outputs of the same kind can be paralleled. In this case the maximum

flyback energy should not exceed the limit value for single output.

The immunity of the circuit with respect to the transients at the output is verified during the characterization for

Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test Pulses are coupled to the outputs with

200pF series capacitor. The correct function of the circuit with the Test Pulses coupled to the outputs is verified

during the characterization for the typical application with R = 16

Ω to 200Ω, L= 0 to 600mH loads. All outputs

withstand testpulses without damage.

BAT

V

R, L loads

µP

U459

VOLTAGE

REGULATOR

DD

V

U459

Diag1

Q1

CSB

SI

SCLK

SO

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

GND

Diag0

Diag7

Reset

Q0

CH0

OT0

Diag6

Q6

Q0

Q7

Diag2

Q2

CH3

CH4

CH5

CH1

Diag3

Q3

Diag4

Q4

Diag5

Q5

Q7

CH7

Diag7

Reset

Reset

Undervoltage

RESET

Q1

Q2

Q3

Q4

Q5

Q6

Diag1

Diag2

Diag3

Diag4

Diag5

Diag6

IOL

24

23

14

13

12

11

2

1

22

9

4

3

10

5 -8

17 - 20

Over

Temperature

Detect

+

-

+

-

=

=

+

-

Gate

Control

OL0

CH2

CH7

SFPD

15

VDG

Diag0

16

VDD