TP70H480G4JSG Datasheet

R07DS1594EU0102 Rev.1.02

Nov 21, 2025

Page 5

2.3

Electrical Specifications – Forward Device

TJ = 25°C unless otherwise stated.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Unit

VDSS(BL)

Maximum drain-source voltage

VGS = 0V

700

-

-

V

VGS(th)

Gate threshold voltage

VDS = VGS, ID = 0.5mA

3.1

3.6

4.1

V

ΔVGS(th)/TJ

Gate threshold voltage temperature

coefficient

-

-5.8

-

mV/°C

RDS(on)eff

Drain-source on-resistance [1]

VGS = 6V, ID = 3A

-

480

560

mΩ

VGS = 6V, ID = 3A,

TJ = 150°C

-

1000

-

IDSS

Drain-to-source leakage current

VDS = 700V, VGS = 0V

-

1

10

µA

VDS = 700V, VGS = 0V,

TJ = 150°C

-

5

-

IGSS

Gate-to-source forward leakage current [2]

VGS = 20V

-

-

10

µA

Gate-to-source reverse leakage current [2]

VGS = -20V

-

-

-10

IGSS

Gate-to-source forward leakage current [2]

VGS = 6V

-

-

0.1

µA

Gate-to-source reverse leakage current [2]

VGS = -6V

-

-

-0.1

CISS

Input capacitance

VGS = 0V, VDS = 400V,

f = 1MHz

-

465

-

pF

COSS

Output capacitance

-

8

-

CRSS

Reverse transfer capacitance

-

1.2

-

CO(er)

Output capacitance, energy related [3]

VGS = 0V, VDS = 0V to

400V

-

11.6

-

pF

CO(tr)

Output capacitance, time related [4]

-

23

-

QG

Total gate charge

VDS = 400V, VGS = 0V to

6V, ID = 3A

-

5.2

-

nC

QGS

Gate-source charge

-

1.3

-

QGD

Gate-drain charge

-

2.1

-

QOSS

Output charge

VGS = 0V, VDS = 0V to

400V

-

9.2

-

nC

tD(on)

Turn-on delay

VDS = 400V, VGS = 0V to

6V, ID = 3A, RG = 20Ω,

ZFB = 120Ω at 100MHz

(see Figure 15)

-

23.2

-

ns

tR

Rise time

-

3

-

tD(off)

Turn-off delay

-

53.6

-

tF

Fall time

-

10

-

1.

Dynamic RDS(on),100% tested; see Figure 17 and Figure 18 for conditions.

2.

Including leakage current of the integrated ESD protection circuit.

3.

Equivalent capacitance to give same stored energy from 0V to 400V.

4.

Equivalent capacitance to give same charging time from 0V to 400V.