Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

CY7C60445 Datasheet(PDF) 21 Page - Cypress Semiconductor

Part # CY7C60445
Description  enCoRe??V Low Voltage Microcontroller
PDF  26 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C60445 Datasheet(HTML) 21 Page - Cypress Semiconductor

Back Button CY7C60445 Datasheet HTML 17Page - Cypress Semiconductor CY7C60445 Datasheet HTML 18Page - Cypress Semiconductor CY7C60445 Datasheet HTML 19Page - Cypress Semiconductor CY7C60445 Datasheet HTML 20Page - Cypress Semiconductor CY7C60445 Datasheet HTML 21Page - Cypress Semiconductor CY7C60445 Datasheet HTML 22Page - Cypress Semiconductor CY7C60445 Datasheet HTML 23Page - Cypress Semiconductor CY7C60445 Datasheet HTML 24Page - Cypress Semiconductor CY7C60445 Datasheet HTML 25Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 26 page
background image
PRELIMINARY
CY7C60445, CY7C6045x
Document Number: 001-12395 Rev. *E
Page 21 of 26
Figure 7. GPIO Timing Diagram
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
TFall
TRise023
TRise1
90%
10%
GPIO
Pin
Output
Voltage
Table 12. AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.750
–
25.2
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–ns
–
Power Up IMO to Switch
150
–
–
μs
Table 13. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
–
18
ms
TWRITE
Flash Block Write Time
–
–
25
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
TDSCLK2
Data Out Delay from Falling Edge of SCLK
–
–
70
ns
[+] Feedback



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com