STA8135G datasheet(18/41 Pages) STMICROELECTRONICS

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3.16

Direct memory access (DMA)

The DMAC is an advanced microcontroller bus architecture (AMBA) compliant to System-on-Chip (SoC)

peripheral. The DMAC is an AMBA AHB module, and connects to the advanced high-performance bus (AHB).

Module key features:

•

Eight DMA channels. Each channel can support an unidirectional transfer.

•

The DMAC provides 32 peripheral DMA request lines.

•

Single DMA and burst DMA request signals.

•

Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers.

•

Scatter or gather DMA support through the use of linked lists.

•

Hardware DMA channel priority. DMA channel 0 has the highest priority and channel 31 has the lowest

priority.

•

If requests from two channels become active at the same time, the channel with the highest priority is

serviced first.

•

AHB slave DMA programming interface to the DMA control registers.

•

Two AHB bus masters for transferring data.

•

Programmable DMA burst size.

•

Working on AHB clock.

3.17

Temperature sensor

Temperature measurement range is -40 to 85 °C. It uses integrated bandgap reference and 8-bit ADC.

The temperature sensor provides two threshold registers. Writing in these registers and enabling the threshold

mode compare the temperature recorded with the threshold value. If the temperature is higher than the upper

threshold register or lower than the lower threshold register, it generates an interrupt if enabled.

Table 11. Temperature sensor

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

Tsens

Sensitivity

°C

Tacc(1)

Accuracy

Calibration performed at Ta = 85 °C °C

±3(2)

± 10

°C

1. Best accuracy is at calibrated temperature.

2. Limited by manufacturing calibration environment.

3.18

Serial boot pins

UART2-TX (Boot0) pin is used to select the boot configuration of Cortex® M7. The ROM code starts the boot

process which then polls the PRCC register (UART2-TX) which has already latched the UART2-TX pin (E2 ball)

status after latch reset.

Based on this register value the code is loaded from one of the two options as given in the table below:

Table 12. Boot peripheral selection

ROM action

UART2-TX = 0

Boot from flash memory - SFC controller

UART2-TX = 1

Boot from peripheral - UART

3.19

Reset

After a reset, the Cortex® M7 is woken-up by the ROM code.

The PRCC module is used to sequence through all the steps needed to properly reset the device and prepare it to

fetch the first instruction of the user application code.

STA8135G has the following reset options:

•

Pad reset: SoC will have active low chip reset (RESET) pad. Low (zero) status on this pad will keep device

in the reset. Assertion of this pin low should be minimum of 5 ms.

STA8135G

General description

DS14788 - Rev 1

page 18/41

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