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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *B
Page 15 of 19
Notes:
35. “X” = “Don’t Care”, “H” = VIH, “L” = VIL.
36. ADS, CNTEN, CNTRST = “Don’t Care”.
37. OE is an asynchronous input signal.
38. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
39. CE0 and OE = VIL; CE1 and R/W = VIH.
40. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
41. Counter operation is independent of CE0 and CE1.
Read/Write and Enable Operation[35, 36, 37]
Inputs
Outputs
OE
CLK
CE0
CE1
R/W
I/O0–I/O17
Operation
X
H
X
X
High-Z
Deselected[38]
X
X
L
X
High-Z
Deselected[38]
X
L
H
L
DIN
Write
L
L
H
H
DOUT
Read[35]
H
X
L
H
X
High-Z
Outputs Disabled
Address Counter Control Operation[35, 39, 40, 41]
Address
Previous
Address
CLK
ADS
CNTEN CNTRST
I/O
Mode
Operation
X
X
X
X
L
Dout(0)
Reset
Counter Reset to Address 0
An
X
L
X
H
Dout(n)
Load
Address Load into Counter
X
An
H
H
H
Dout(n)
Hold
External Address Blocked—Counter
Disabled
X
An
H
L
H
Dout(n+1)
Increment
Counter Enabled—Internal Address
Generation
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