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N74F114D Datasheet(PDF) 3 Page - NXP Semiconductors

Part # N74F114D
Description  Dual J-K negative edge-triggered flip-flop with common clock and reset
PDF  6 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

N74F114D Datasheet(HTML) 3 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74F114
Dual J-K negative edge-triggered flip-flop
with common clock and reset
1996 Mar 14
3
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5.0
5.5
V
VIH
High-level input voltage
2.0
V
VIL
Low-level input voltage
0.8
V
IIK
Input clamp current
–18
mA
IOH
High-level output current
–1
mA
IOL
Low-level output current
20
mA
Tamb
Operating free-air temperature range
0
+70
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS1
MIN
TYP2
MAX
UNIT
VOH
High-level output voltage
VCC = MIN, VIL = MAX
±10%VCC
2.5
V
VOH
High-level output voltage
VIH = MIN, IOH = MAX
±5%VCC
2.7
3.4
V
VOL
Low-level output voltage
VCC = MIN, VIL = MAX
±10%VCC
0.35
0.50
V
VOL
Low-level output voltage
VIH = MIN, IOL = MAX
±5%VCC
0.35
0.50
V
VIK
Input clamp voltage
VCC = MIN, II = IIK
–0.73
–1.2
V
II
Input current at maximum input voltage
VCC = MAX, VI = 7.0V
100
µA
IIH
High-level input current
VCC = MAX, VI = 2.7V
20
µA
I
Lll i
Jn, Kn
V
MAX V
0 5V
–0.6
mA
IIL
Low-level input current
CP
VCC = MAX VI =0 5V
–4.8
mA
IIL
Low-level input current
SDn
VCC = MAX, VI = 0.5V
–3.0
mA
RD
–6.0
mA
IOS
Short-circuit output current3
VCC = MAX
–60
–150
mA
ICC
Supply current (total)4
VCC = MAX
15
21
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Measure ICC with the clock input grounded and all outputs open, with the Q and Q outputs High in turn.



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