TMS320C6000GDP167 datasheet(13/148 Pages) TI

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TMS320C6713

FLOATINGPOINT DIGITAL SIGNAL PROCESSOR

SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

functional block and CPU (DSP core) diagram

Test

C67x

 CPU

Data Path B

B Register File

Instruction Fetch

Instruction Dispatch

Instruction Decode

Data Path A

A Register File

Power-Down

Logic

.L1† .S1† .M1† .D1

.D2 .M2† .S2† .L2†

L1P Cache

Direct Mapped

4K Bytes Total

Control

Registers

Control

Logic

L1D Cache

2-Way

Set Associative

4K Bytes

In-Circuit

Emulation

Interrupt

Control

C6713 Digital Signal Processor

† In addition to fixed-point instructions, these functional units execute floating-point instructions.

Enhanced

DMA

Controller

(16 channel)

L2 Cache/

Memory

4 Banks

64K Bytes

Total

(up to

4-Way)

Clock Generator and PLL

x4 through x25 Multiplier

/1 through /32 Dividers

Memory

192K

Bytes

EMIF

McASP1

McASP0

McBSP1

McBSP0

I2C1

I2C0

Timer 1

Timer 0

GPIO

HPI

McBSPs interface to:

−SPI Control Port

−High-Speed TDM Codecs

−AC97 Codecs

−Serial EEPROM

EMIF interfaces to:

−SDRAM

−SBSRAM

−SRAM,

−ROM/Flash, and

−I/O devices

McASPs interface to:

−I2S Multichannel ADC, DAC, Codec, DIR

−DIT: Multiple Outputs

TMS320C6000GDP167 Datasheet(PDF) 13 Page - Texas Instruments

TMS320C6000GDP167 Datasheet(HTML) 13 Page - Texas Instruments

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