EP2S180 datasheet(39/58 Pages) ALTERA

39 / 58 page

Altera Corporation

Core Version a.b.c variable

2–31

Stratix II EP2S180 DSP Development Board Reference Manual

Board Components & Interfaces

Ethernet MAC/PHY (U16)

The LAN91C111 (U16) is a mixed signal analog/digital device that

implements protocols at 10 Mbps and 100 Mbps. The control pins of U16

are connected to the Stratix II device so that user logic (e.g., the Nios II

processor) can access Ethernet via the RJ-45 connector (RJ1). Refer to

Table 2–26 for Stratix II pin-outs for Ethernet MAC/PHY device U16.t

Table 2–26. Ethernet MAC/PHY (U16) (Part 1

of 3)

Pin Name

Pin Number

ENET_ADS_N

AA25

ENET_AEN

AC25

ENET_BE_N0

AE26

ENET_BE_N1

AE25

ENET_BE_N2

AD25

ENET_BE_N3

AD24

ENET_DATACS_N

T20

ENET_INTRQ0

AB23

ENET_IOCHRDY

V26

ENET_IOR_N

AC24

ENET_IOW_N

AB26

ENET_LDEV_N

T26

enet_RESET_n

ENET_SRDY_N

T25

ENET_W_R_N

T21

SE_A0

AD8

SE_A1

AM27

SE_A2

AM28

SE_A3

AJ27

SE_A4

AK27

SE_A5

AL29

SE_A6

AM29

SE_A7

AJ28

SE_A8

AH28

SE_A9

AK20

SE_A10

AJ20

SE_A11

AL21

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