6.42

15

7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Feb.14.20

Waveform of Interrupt Timing(1)

Truth Table III — Interrupt Flag(1,4)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

NOTES:

1. Assumes BUSYL = BUSYR = VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTR and INTL must be initialized at power-up.

2738 drw 17

ADDR"A"

INTERRUPT SET ADDRESS

(2)

CE"A"

R/

W"A"

tAS

(3)

tWC

tWR

(4)

tINS

(3)

INT"B"

2738 drw 18

ADDR"B"

INTERRUPT CLEAR ADDRESS

(2)

CE"B"

OE"B"

tAS

(3)

tRC

tINR

(3)

INT"B"

Left Port

Right Port

Function

R/WL

CEL

OEL

A12L-A0L

INTL

R/WR

CER

OER

A12R-A0R

INTR

L

L

X

1FFF

XXXX

X

L(2)

Set Right INTR Flag

X

X

XXX

X

L

L

1FFF

H(3)

Reset Right INTR Flag

XX

X

X

L(3)

L

L

X

1FFE

X

Set Left INTL Flag

X

LL1FFE

H(2)

X

X

XXX

Reset Left INTL Flag

2738 tbl 17