M25P05-AVMP6TP datasheet(25/52 Pages) NUMONYX

Part #	M25P05-AVMP6TP

Description	512 Kbit, serial Flash memory, 50 MHz SPI bus interface

PDF	52 Pages

Scroll/Zoom	100%

Manufacturer	NUMONYX [Numonyx B.V]

Direct Link	http://www.numonyx.com

Logo

25 / 52 page

M25P05-A

Instructions

25/52

Table 7.

Protection modes

signal

SRWD

bit

Mode

Write protection of the status

Memory content

Protected

area(1)

As defined by the values in the block protect (BP1, BP0) bits of the status register, as shown in Table 2.

Unprotected

area(1)

Software

protected

(SPM)

Status register is writable (if the

WREN instruction has set the WEL

bit).

The values in the SRWD, BP1 and

BP0 bits can be changed

Protected

against page

program, sector

erase and bulk

erase

Ready to

accept page

program and

sector erase

instructions

Hardware

protected

(HPM)

Status register is hardware write

protected.

The values in the SRWD BP1 and

BP0 bits cannot be changed

Protected

against page

program, sector

erase and bulk

erase

Ready to

accept page

program and

sector erase

instructions

M25P05-AVMP6TP Datasheet(PDF) 25 Page - Numonyx B.V

M25P05-AVMP6TP Datasheet(HTML) 25 Page - Numonyx B.V

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL