M25P16-VMP6TP datasheet(23/55 Pages) NUMONYX

Part #	M25P16-VMP6TP

Description	16 Mbit, serial Flash memory, 75 MHz SPI bus interface

PDF	55 Pages

Scroll/Zoom	100%

Manufacturer	NUMONYX [Numonyx B.V]

Direct Link	http://www.numonyx.com

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23 / 55 page

M25P16

Instructions

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6.4.4

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware Protected mode (when the Status Register

Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W) is driven Low). In this mode, the

non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and

the Write Status Register (WRSR) instruction is no longer accepted for execution.

Figure 11.

Read Status Register (RDSR) instruction sequence and data-out

sequence

3456789 10 11 12 13 14 15

Instruction

AI02031E

6543210

Status Register Out

High Impedance

MSB

6543210

Status Register Out

MSB

M25P16-VMP6TP Datasheet(PDF) 23 Page - Numonyx B.V