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M25PE40-VMP6TP Datasheet(PDF) 51 Page - Numonyx B.V

Part # M25PE40-VMP6TP
Description  4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout
PDF  62 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M25PE40-VMP6TP Datasheet(HTML) 51 Page - Numonyx B.V

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M25PE40
DC and AC parameters
51/62
Table 22.
AC characteristics (75 MHz operation, T9HX (0.11µm) process(1))(2)(3)(4)
Test conditions specified in Table 14 and Table 15
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
fC
fC
Clock frequency for the following instructions:
FAST_READ, RDLR, PW, PP, WRLR, PE, SE,
SSE, DP, RDP, WREN, WRDI, RDSR, WRSR
D.C.
75
MHz
fR
Clock frequency for READ instructions
D.C.
33
MHz
tCH
(5)
tCLH
Clock High time
6
ns
tCL
(5)
tCLL
Clock Low time
6
ns
Clock Slew Rate (peak to peak)
0.1
V/ns
tSLCH
tCSS
S Active Setup time (relative to C)
5
ns
tCHSL
S Not Active Hold time (relative to C)
5
ns
tDVCH
tDSU
Data In Setup time
2
ns
tCHDX
tDH
Data In Hold time
5
ns
tCHSH
S Active Hold time (relative to C)
5
ns
tSHCH
S Not Active Setup time (relative to C)
5
ns
tSHSL
tCSH
S Deselect time
100
ns
tSHQZ
(6)
tDIS
Output Disable time
8
ns
tCLQV
tV
Clock Low to Output Valid
8/6
ns
tCLQX
tHO
Output Hold time
0
ns
tWHSL
(7)
Write Protect Setup time
20
ns
tSHWL
(7)
Write Protect Hold time
100
ns
tDP
(6)
S to Deep Power-down
3
µs
tRDP
(6)
S High to Standby mode
30
µs
tW
Write Status Register cycle time
3
15
ms
tPW
(8)
Page Write cycle time (256 bytes)
11
23
ms
tPP
(8)
Page Program cycle time (256 bytes)
0.8
3ms
Page Program cycle time (n bytes)
int(n/8) ×
0.025(9)
tPE
Page Erase cycle time
10
20
ms
tSE
Sector Erase cycle time
1.5
5
s
tSSE
Subsector Erase cycle time
80
150
ms
tBE
Bulk Erase cycle time
8
10
s
1.
See Important note on page 6.
2.
Details of how to find the technology process in the marking are given in AN1995, see also Section 13: Ordering
information.
3.
Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008.
4.
Preliminary data.
5.
tCH + tCL must be greater than or equal to 1/ fC.
6.
Value guaranteed by characterization, not 100% tested in production.
7.
Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.



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