1

Jun.16.21

HIGH SPEED

2K X 16 DUAL-PORT

SRAM

7133SA/LA

7143SA/LA

Features

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High-speed access

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Commercial:20/25/35/45/55/70/90ns(max.)

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Industrial: 25ns (max.)

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Military:35/55/70/90ns(max.)

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Low-power operation

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IDT7133/43SA

Active: 1150mW (typ.)

Standby: 5mW (typ.)

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IDT7133/43LA

Active: 1050mW (typ.)

Standby: 1mW (typ.)

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Versatile control for write: separate write control for lower

and upper byte of each port

Functional Block Diagram

NOTE:

1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.

IDT7143 (SLAVE): BUSY is input.

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MASTER IDT7133 easily expands data bus width to 32 bits

or more using SLAVE IDT7143

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On-chip port arbitration logic (IDT7133 only)

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BUSY output flag on IDT7133; BUSY input on IDT7143

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Fully asynchronous operation from either port

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Battery backup operation–2V data retention

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TTL-compatible; single 5V (±10%) power supply

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Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-

pin TQFP

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Military product compliant to MIL-PRF-38535 QML

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Industrial temperature range (–40°C to +85°C) is available

for selected speeds

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Green parts available, see ordering information

I/O

CONTROL

MEMORY

ARRAY

ARBITRATION

LOGIC

(IDT7133 ONLY)

R/

WLUB

CEL

R/

WLLB

OEL

I/O0L -I/O7L

BUSYL

A0L

CEL

R/

WRUB

CER

R/

WRLB

OER

I/O8R -I/O15R

I/O0R -I/O7R

BUSYR

(1)

A0R

CER

2746 drw 01

A10L

ADDRESS

DECODER

A10R

I/O

CONTROL

ADDRESS

DECODER

11

11

(1)

I/O8L -I/O15L