M28W640HCT datasheet(14/72 Pages) NUMONYX

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Bus operations

M28W640HCT, M28W640HCB

14/72

Bus operations

There are six standard bus operations that control the device. These are Bus Read, Bus

Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2: Bus operations,

for a summary.

Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the

memory and do not affect bus operations.

3.1

Read

Read bus operations are used to output the contents of the memory array, the Electronic

Signature, the Status Register and the common Flash interface. Both Chip Enable and

Output Enable must be at VIL in order to perform a read operation. The Chip Enable input

should be used to enable the device. Output Enable should be used to gate data onto the

output. The data read depends on the previous command written to the memory (see

Section 4: Command interface). See Figure 8: Read AC waveforms, and Table 16: Read AC

characteristics, for details of when the output becomes valid.

Read operations of the memory array can be performed in asynchronous page mode, which

provides a fast access time. Data is internally read and stored in a page buffer. The page

has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the

electronic signature, the Status Register, the command Flash interface, the Block Protection

status, the Configuration Register status and the security code are performed as

asynchronous read cycles (Random Read). Both Chip Enable, E, and Output Enable, G,

must be at VIL in order to read the output of the memory (see Figure 9: Page Read AC

waveforms).

Read mode is the default state of the device when exiting reset or after power-up.

3.2

Write

Bus write operations write commands to the memory or latch input data to be programmed.

A write operation is initiated when Chip Enable and Write Enable are at VIL with Output

Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write

Enable or Chip Enable, whichever occurs first.

See Figure 9 and Figure 11, Write AC waveforms, and Table 17 and Table 18, Write AC

characteristics, for details of the timing requirements.

3.3

Output Disable

The data outputs are high impedance when the Output Enable is at VIH.

3.4

Standby

Standby disables most of the internal circuitry allowing a substantial reduction of the current

consumption. The memory is in standby when Chip Enable is at VIH and the device is in

read mode. The power consumption is reduced to the standby level and the outputs are set

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