AT25SF641B datasheet(39/62 Pages) RENESAS

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DS-AT25SF641B-191 Rev. K

Page 39

2025-12-12

AT25SF641B Datasheet

11. Status Register Commands

11.1 Read Status Register (05h, 35h, and 15h)

The Status Register can be read to determine the device's ready/busy status, as well as the status of many other

functions, such as Block Protection. The Status Register can be read at any time, including during an internally

self-timed program or erase operation.

To read Status Register Byte 1, the CS pin must first be asserted and the opcode of 05h must be clocked into the

device. After the opcode has been clocked in, the device begins outputting Status Register Byte 1 data on the SO

pin during every subsequent clock cycle. After the last bit (0) of Status Register Byte 1 has been clocked out, the

sequence repeats itself, starting again with bit 7, as long as the CS pin remains asserted and the clock pin is being

pulsed. The data in the Status Register is constantly being updated, so each repeating sequence outputs new

data. Deasserting the CS pin terminates the Read Status Register operation and puts the SO pin into a high-

impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

To read Status Register Byte 2, the CS pin must first be asserted, and the opcode of 35h must be clocked into the

device. After the opcode has been clocked in, the device begins outputting Status Register Byte 2 data on the SO

pin during every subsequent clock cycle. After the last bit (0) of Status Register Byte 2 has been clocked out, the

sequence repeats itself starting again with bit 7 as long as the CS pin remains asserted and the clock pin is being

pulsed. The data in the Status Register is constantly being updated, so each repeating sequence outputs new

data. Deasserting the CS pin terminates the Read Status Register operation and puts the SO pin into a high-

impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

1. Only bits designated as R/W can be modified when using the Write Status Register command. Bits designated as R cannot be modified.

2. R/W = Readable and writable; R = Readable only.

Table 11. Status Register 1 Bit Assignments

Bit1

Mnemonic

Name

Type2

Description

SRP0

Status Register Protection bit 0

R/W

See Table 15 on Status Register Protection.

BP4

Block Protection bit 4

R/W

See Table 6 and Table 7 on Non-Volatile Protection.

BP3

Block Protection bit 3

R/W

BP2

Block Protection bit 2

R/W

BP1

Block Protection bit 1

R/W

BP0

Block Protection bit 0

R/W

WEL

Write Enable Latch Status

Device is not Write Enabled (default).

Device is Write Enabled.

0RDY/BSY

Ready/Busy Status

Device is ready.

Device is busy with an internal operation.

AT25SF641B Datasheet(PDF) 39 Page - Renesas Technology Corp

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