M14256 datasheet(6/12 Pages) STMICROELECTRONICS

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M14256, M14128

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Figure 6. Write Mode Sequences with WC=0

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

AI01106B

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

R/W

ACK

R/W

ACK

Table 6. Operating Modes

Note: 1. X =

VIH or VIL.

Mode

RW bit

WC 1

Bytes

Initial Sequence

Current Address Read

‘1’

START, Device Select, RW = ‘1’

Random Address Read

‘0’

START, Device Select, RW = ‘0’, Address

‘1’

reSTART, Device Select, RW = ‘1’

Sequential Read

‘1’

≥ 1

Similar to Current or Random Mode

Byte Write

‘0’

VIL

START, Device Select, RW = ‘0’

Page Write

‘0’

VIL

≤ 64

START, Device Select, RW = ‘0’

byte or page write mode, the generation by the

master of the STOP condition starts the internal

memory program cycle. This STOP condition trig-

gers an internal memory program cycle only if the

STOP condition is internally decoded immediately

after the ACK bit; any STOP condition decoded

out of this "10th bit" time slot will not trigger the in-

ternal programming cycle. All inputs are disabled

until the completion of this cycle and the Memory

will not respond to any request.

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