AT45DB641E-DWF datasheet(38/78 Pages) RENESAS

38 / 78 page

DS-AT45DB641E-027 Rev. O

Page 38

6/30/23

AT45DB641E Datasheet

10. Additional Commands

10.1 Main Memory Page to Buffer Transfer

A page of data can be transferred from the main memory to either Buffer 1 or Buffer 2. To transfer a page of data

using the standard DataFlash page size (264 bytes), an opcode of 53h for Buffer 1 or 55h for Buffer 2 must be

clocked into the device followed by three address bytes comprised of 15 page address bits (PA14 - PA0) which

specify the page in main memory to be transferred, and 9 dummy bits. To transfer a page of data using the binary

page size (256 bytes), an opcode of 53h for Buffer 1 and 55h for Buffer 2 must be clocked into the device followed

by three address bytes comprised of 1 dummy bit, 15 page address bits (A22 - A8) which specify the page in the

main memory to be transferred, and 8 dummy bits.

The CS pin must be low while toggling the SCK pin to load the opcode and the three address bytes from the input

pin (SI). The transfer of the page of data from the main memory to the buffer begins when the CS pin transitions

from a low to a high state. During the page transfer time (tXFR), the RDY/BUSY bit in the Status Register can be

read to determine whether or not the transfer has been completed.

10.2 Main Memory Page to Buffer Compare

A page of data in main memory can be compared to the data in Buffer 1 or Buffer 2 as a method to ensure that

data were successfully programmed after a Buffer to Main Memory Page Program command. To compare a page

of data with the standard DataFlash page size (264 bytes), an opcode of 60h for Buffer 1 or 61h for Buffer 2 must

be clocked into the device followed by three address bytes comprised of 15 page address bits (PA14 - PA0) which

specify the page in the main memory to be compared to the buffer, and 9 dummy bits. To compare a page of data

with the binary page size (256 bytes), an opcode of 60h for Buffer 1 or 61h for Buffer 2 must be clocked into the

device followed by three address bytes comprised of 1 dummy bit, 15 page address bits (A22 - A8) which specify

the page in the main memory to be compared to the buffer, and 8 dummy bits.

The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin

(SI). On the low-to-high transition of the CS pin, the data bytes in the selected Main Memory Page are compared

with the data bytes in Buffer 1 or Buffer 2. During the compare time (tCOMP), the RDY/BUSY bit in the Status

updated with the result of the compare.

AT45DB641E-DWF Datasheet(PDF) 38 Page - Renesas Technology Corp