REJ03D0619-0300 Rev.3.00 Mar 25, 2009

Page 1 of 9

HD74HC373, HD74HC533

Octal D-type Transparent Latches (with 3-state outputs)

Octal D-type Transparent Latches (with inverted 3-state outputs)

REJ03D0619-0300

Rev.3.00

Mar 25, 2009

Description

When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of

HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be

retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control

input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of

the storage elements.

Features

• High Speed Operation: t

pd (D to Q) = 16 ns typ (CL = 50 pF)

• High Output Current: Fanout of 15 LSTTL Loads

• Wide Operating Voltage: V

CC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: I

CC (static) = 4

µA max (Ta = 25°C)

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74HC373P

HD74HC533P

DILP-20 pin

PRDP0020AC-B

(DP-20NEV)

P

—

HD74HC373FPEL

HD74HC533FPEL

SOP-20 pin (JEITA)

PRSP0020DD-B

(FP-20DAV)

FP

EL (2,000 pcs/reel)

HD74HC373RPEL

HD74HC533RPEL

SOP-20 pin (JEDEC)

PRSP0020DC-A

(FP-20DBV)

RP

EL (1,000 pcs/reel)

HD74HC373TELL

TSSOP-20 pin

PTSP0020JB-A

(TTP-20DAV)

T

ELL (2,000 pcs/reel)

Note:

Please consult the sales office for the above package availability.

Function Table

Output Control

Enable G

D

HD74HC373

Q

HD74HC533

Q

L

H

H

H

L

L

H

L

L

H

L

L

X

No change

No change

H

X

X

Z

Z

Note:

1. H; High level, L; Low level, X; Irrelevant, Z; High impedance