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NAND02G-B2D Datasheet(PDF) 13 Page - Numonyx B.V

Part # NAND02G-B2D
Description  2-Gbit, 2112-byte/1056-word page multiplane architecture, 1.8 V or 3 V, NAND flash memories
PDF  69 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

NAND02G-B2D Datasheet(HTML) 13 Page - Numonyx B.V

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NAND02G-B2D
Memory array organization
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Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series. It
is organized into blocks where each block contains 64 pages. The array is split into two
areas, the main area and the spare area. The main area of the array is used to store data,
and the spare area typically stores error correction codes, software flag, or bad block
identification.
In x 8 devices, the pages are split into a 2048-byte main area and a spare area of 64 bytes.
In x 16 devices, the pages are split into a 1024-word main area and a spare area of
32 words. Refer to Figure 5: Memory array organization.
Bad blocks
In the x8 devices, the NAND flash 2112-byte/1056-word page devices may contain bad
blocks, which are blocks that contain one or more invalid bits whose reliability is not
guaranteed. Additional bad blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 8.1: Bad block
management for more details).
There are a minimum of 2008 and a maximum of 2048 valid blocks. These numbers include
both the bad blocks that are present when the device is shipped and the bad blocks that
could develop later on.
These blocks need to be managed using bad blocks management, block replacement, or
error correction codes (refer to Section 8: Software algorithms).



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