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PIC16F62X Datasheet(PDF) 13 Page - Microchip Technology

Part # PIC16F62X
Description  Silicon/Data Sheet Errata
PDF  20 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
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PIC16F62X Datasheet(HTML) 13 Page - Microchip Technology

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© 2002 Microchip Technology Inc.
DS80073F-page 13
PIC16F62X
17.3
DC Characteristics: PIC16F62X (Commercial, Industrial, Extended)
PIC16LF62X (Commercial, Industrial)
DC Characteristics
Standard Operating Conditions (unless otherwise stated)
Operating temperature
–40°C
≤ TA ≤ +85°C for industrial and
0°C
≤ TA ≤ +70°C for commercial and
–40°C
≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Table 17-1 and Table 12-2
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Unit Conditions
VIL
Input Low Voltage
I/O ports:
D030
with TTL buffer
VSS
—0.8
0.15 VDD
VVDD = 4.5V to 5.5V
otherwise
D031
with Schmitt Trigger input
VSS
0.2 VDD
V
D032
MCLR, RA4/T0CKI,OSC1 (in ER
mode)
VSS
—
0.2 VDD
V
D033
OSC1 (in XT and HS)
VSS
—
0.3 VDD
V
OSC1 (in LP)
VSS
—
0.6 VDD-1.0
V
VIH
Input High Voltage
I/O ports:
—
D040
with TTL buffer
2.0V
.25 VDD + 0.8V
—VDD
VDD
VVDD = 4.5V to 5.5V
otherwise
D041
with Schmitt Trigger input
0.8 VDD
—VDD
D042
MCLR RA4/T0CKI
OSC1 (EC mode)
0.8 VDD
0.8 VDD
—
—
VDD
VDD
V
V
D043
OSC1 (XT, HS and LP)
0.7 VDD
—VDD
V
D070
IPURB
PORTB weak pull-up current
50
200
400
µAVDD = 5.0V, VPIN = VSS
IIL
Input Leakage Current(1), (2)
I/O ports (except PORTA)
±1.0
µAVSS ≤ VPIN ≤ VDD, pin at hi-impedance
D060
PORTA
—
—
±0.5
µAVSS ≤ VPIN ≤ VDD, pin at hi-impedance
D061
RA4/T0CKI
—
—
±1.0
µAVSS ≤ VPIN ≤ VDD
D063
OSC1, MCLR
——
±5.0
µAVSS ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
VOL
Output Low Voltage
D080
I/O ports
—
—
0.6
V
IOL=8.5 mA, VDD=4.5V, -40
° to +85°C
——
0.6
V
IOL=7.0 mA, VDD=4.5V, +125
°C
D083
OSC2/CLKOUT (ER only)
—
—
0.6
V
IOL=1.6 mA, VDD=4.5V, -40
° to +85°C
——
0.6
V
IOL=1.2 mA, VDD=4.5V, +125
°C
VOH
Output High Voltage(2)
D090
I/O ports (except RA4)
VDD-0.7
—
—
V
IOH=-3.0 mA, VDD=4.5V, -40
° to +85°C
VDD-0.7
—
—
V
IOH=-2.5 mA, VDD=4.5V, +125
°C
D092
OSC2/CLKOUT (ER only)
VDD-0.7
—
—
V
IOH=-1.3 mA, VDD=4.5V, -40
° to +85°C
VDD-0.7
—
—
V
IOH=-1.0 mA, VDD=4.5V, +125
°C
*D150
VOD
Open Drain High Voltage
—
8.5*
V
RA4 pin PIC16F62X, PIC16LF62X
Capacitive Loading Specs on Out-
put Pins
D100
COSC2 OSC2 pin
—
15
pF
In XT, HS and LP modes when external
clock used to drive OSC1
D101
CIO
All I/O pins/OSC2 (in ER mode)
—
50
pF
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25
°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note
1:
The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operat-
ing conditions. Higher leakage current may be measured at different input voltages.
2:
Negative current is defined as coming out of the pin.



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