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NAND16GAH0D Datasheet(PDF) 21 Page - Numonyx B.V |
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NAND16GAH0D Datasheet(HTML) 21 Page - Numonyx B.V |
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21 / 116 page ![]() NAND08GAH0A, NAND16GAH0D MultiMediaCard interface 21/116 4.4 Electrical specifications Table 6 defines the bus operating conditions for the device. The total capacitance CL of each line of the bus is given by the below equation: where CHOST is the bus master capacitance, CBUS the bus capacitance itself and CCARD the capacitance of the device connected to this line. The sum of the host and bus capacitance, CHOST+CBUS, must not to exceed 20 pF. As the bus can be supplied with a variable supply voltage, all bus signal levels are related to the supply voltage (see Figure 8, Table 7, and Table 8). C L C HOST C BUS C CARD ++ = Table 6. Bus operating conditions(1)(2) Symbol Parameter Min Max Unit Peak voltage on all lines −0.5 3.6 V Input leakage current on all inputs (before initialization sequence and/or internal pull up resistors connected)(3) −100 100 µA Input leakage current on all inputs (after initialization sequence and/or internal pull up resistors connected)(3) −10 10 µA Output leakage current on all outputs (before initialization sequence) −100 100 µA Output leakage current on all outputs (after initialization sequence) −10 10 µA VCCQ Low supply-voltage range (MultiMediaCard v. 4.1) 1.65 1.95 V High supply-voltage range 2.7 3.6 VCC Input/output supply voltage 2.7 3.6 V VSS Supply voltage ground −0.5 0.5 V RDAT Pull-up resistance (to prevent bus floating) 50 100 k Ω RCMD Pull-up resistance (to prevent bus floating) 4.7 100 k Ω RINT Internal pull up resistance DAT1-DAT7 (to prevent unconnected line floating) 50 150 k Ω R4 Load resistance on VCC line after power-up or hot insertion 330 Ω C4 Load capacitance on VCC line after power-up or hot insertion 10 µF CL Bus signal line capacitance 30 pF CCARD Single card capacitance 7 pF C1 Load capacitance on CMD input TBD TBD pF C2 Load capacitance on DAT input TBD TBD pF C3 Load capacitance on CLK input TBD TBD pF C5 Decoupling capacitance on VCCI input 1 pF Maximum signal line inductance (fPP ≤52 MHz) 16 nH 1. The current consumption of the device for the different configurations is defined in the POWER_CLASS field of the EXT_CSD register (see Section 8.4). 2. TBD stands for ‘to be defined’. 3. See Section 4.3: Power-up and power-down. |
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