Figure 15-1.
Ethernet Controller Block Diagram .................................................................................. 364
Figure 15-2.
Ethernet Controller ......................................................................................................... 364
Figure 15-3.
Ethernet Frame ............................................................................................................. 366
Figure 16-1.
Analog Comparator Module Block Diagram ..................................................................... 408
Figure 16-2.
Structure of Comparator Unit .......................................................................................... 409
Figure 16-3.
Comparator Internal Reference Structure ........................................................................ 410
Figure 17-1.
PWM Module Block Diagram .......................................................................................... 420
Figure 17-2.
PWM Count-Down Mode ................................................................................................ 421
Figure 17-3.
PWM Count-Up/Down Mode .......................................................................................... 422
Figure 17-4.
PWM Generation Example In Count-Up/Down Mode ....................................................... 422
Figure 17-5.
PWM Dead-Band Generator ........................................................................................... 423
Figure 18-1.
QEI Block Diagram ........................................................................................................ 452
Figure 18-2.
Quadrature Encoder and Velocity Predivider Operation .................................................... 453
Figure 19-1.
Pin Connection Diagram ................................................................................................ 468
Figure 22-1.
Load Conditions ............................................................................................................ 487
Figure 22-2.
I
2C Timing ..................................................................................................................... 489
Figure 22-3.
External XTLP Oscillator Characteristics ......................................................................... 492
Figure 22-4.
Hibernation Module Timing ............................................................................................. 493
Figure 22-5.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 493
Figure 22-6.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 494
Figure 22-7.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 494
Figure 22-8.
JTAG Test Clock Input Timing ......................................................................................... 495
Figure 22-9.
JTAG Test Access Port (TAP) Timing .............................................................................. 496
Figure 22-10. JTAG TRST Timing ........................................................................................................ 496
Figure 22-11. External Reset Timing (RST) ........................................................................................... 497
Figure 22-12. Power-On Reset Timing ................................................................................................. 497
Figure 22-13. Brown-Out Reset Timing ................................................................................................ 497
Figure 22-14. Software Reset Timing ................................................................................................... 498
Figure 22-15. Watchdog Reset Timing ................................................................................................. 498
Figure 23-1.
100-Pin LQFP Package .................................................................................................. 499
9
June 14, 2007
Luminary Micro Confidential-Advance Product Information
LM3S6950 Microcontroller
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