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ISL22326 Datasheet(PDF) 13 Page - Renesas Technology Corp

Part # ISL22326
Description  Dual Digitally Controlled Potentiometers (XDCP™) Low Noise, Low Power, I2C Bus, 128 Taps
PDF  21 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL22326 Datasheet(HTML) 13 Page - Renesas Technology Corp

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FN6176 Rev.4.00
Page 13
Sep 16, 2024
ISL22326 Datasheet
4.2
Bus Interface Pins
4.2.1
Serial Data Input/Output (SDA)
The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code,
wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts
out data after each falling edge of the serial clock.
SDA requires an external pull-up resistor because it is an open-drain input/output.
4.2.2
Serial Clock (SCL)
This is the serial clock input of the I2C serial interface. SCL requires an external pull-up resistor because it is an
open-drain input.
4.2.3
Device Address (A2 - A0)
The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in
the slave address serial data stream must match with the Address input pins to initiate communication with the
ISL22326. A maximum of eight ISL22326 devices may occupy the I2C serial bus.
5.
Principles of Operation
The ISL22326 is an integrated circuit incorporating two DCPs with their associated registers, non-volatile memory
and an I2C serial interface providing direct communication between a host and the potentiometers and memory.
The resistor arrays are comprised of individual resistors connected in series. At either end of the array and
between each resistor is an electronic switch that transfers the potential at that point to the wiper.
The electronic switches on the device operate in a make-before-break mode when the wiper changes tap
positions.
When the device is powered down, the last value stored in IVRi is maintained in the non-volatile memory. When
power is restored, the contents of the IVRi are recalled and loaded into the corresponding WRi to set the wipers to
the initial value.
5.1
DCP Description
Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of
each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of
each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR).
Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0] = 00h), its wiper terminal (RW)
is closest to its Low terminal (RL). When the WR register of a DCP contains all ones (WR[6:0] = 7Fh), its wiper
terminal (RW) is closest to its High terminal (RH). As the value of the WR increases from all zeroes (0) to all ones
(127 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same
time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW
decreases monotonically.
While the ISL22326 is being powered up, all WRs are reset to 40h (64 decimal), which locates RW roughly at the
center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile
memory reading, all WRs are reloaded with the value stored in corresponding non-volatile Initial Value Registers
(IVRs).
The WRs can be read or written to directly using the I2C serial interface as described in the following sections. The
I2C interface Address Byte has to be set to 00h or 01h to access the WR of DCP0 or DCP1 respectively.



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