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M29W040 Datasheet(PDF) 13 Page - STMicroelectronics |
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M29W040 Datasheet(HTML) 13 Page - STMicroelectronics |
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13 / 31 page  Symbol Alt Parameter M29W040 Unit -100 -120 VCC = 3.3V ±0.3V CL = 30pF VCC = 3.3V ±0.3V Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 100 120 ns tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns tWLWH tWP Write Enable Low to Write Enable High 45 50 ns tDVWH tDS Input Valid to Write Enable High 45 50 ns tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low 25 30 ns tAVWL tAS Address Valid to Write Enable Low 0 0 ns tWLAX tAH Write Enable Low to Address Transition 45 50 ns tGHWL Output Enable High to Write Enable Low 0 0 ns tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs tWHQV1 (1) Write Enable High to Output Valid (Program) 12 12 µs tWHQV2 (1) Write Enable High to Output Valid (Block Erase) 1.5 30 1.5 30 sec tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV =tWHQ7V +tQ7VQV. Table 13A. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 °C, –20 to 85°C or –40 to 85°C) Chip Erase(CE) instruction. This instruction uses six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two coded cycles. The Chip Erase Confirm com- mand 10h is written at address5555h on sixth cycle after another two coded cycles. If the second com- mand given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessaryto program the array with 00h first as the P/E.C. will automatically do this before erasing to FFh. Read operations after the sixth rising edge of W or E output the status register bits. During the execu- tion of the erase by the P/E.C. the memory will not accept any instruction. Read of Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle Bit DQ6 toggles during erase operation and stops when erase is com- pleted. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure because the erasure has not been verified even after the maximum number of erase cycles have been executed. 13/31 M29W040 |
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