© 1995 Microchip Technology Inc.

DS11182C-page 3

85C72/82/92

TABLE 1-3:

AC CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Units

Remarks

Clock frequency

—

—

100

kHz

Clock high time

4000

—

—

ns

Clock low time

4700

—

—

ns

SDA and SCL rise time

—

—

1000

ns

SDA and SCL fall time

—

—

300

ns

START condition hold time

4000

—

—

ns

After this period the first

clock pulse is generated

START condition setup time

4700

—

—

ns

Only relevant for repeated

START condition

Data input hold time

0—

—

ns

Data input setup time

250

—

—

ns

Data output delay time

300

—

3500

ns

Note 1

STOP condition setup time

4700

—

—

ns

Bus free time

4700

—

—

ns

Time the bus must be free

before a new transmission

can start

Input filter time constant

(SDA and SCL pins)

—

—

100

ns

Program cycle time

—.4

.4N

1

N

ms

ms

Byte Mode

Page Mode, N = # of bytes

to be written

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

FIGURE 1-2:

BUS TIMING DATA

SU:STA

t

HD:STA

t

F

t

LOW

t

HIGH

t

R

t

SU:STO

t

BUF

t

t

AA

t

SDA

OUT

SDA

IN

SCL

HD:DAT

t

SU:DAT

t

AA