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©2021–2023 Renesas Electronics Corporation

R31DS0066EU0103 May 8, 2023

9SQ445 Datasheet

1 PWRGD/PWRGDN# = 1, all outputs enabled.

2 PWRGD/PWRGDN# = 0.

3 For outputs are driving source-terminated high-impedance loads. Add 7mA for each output at 25M driving a double-terminated load and 2.5mA for

each output at 100M driving a double-terminated load.

1 Peak-to-peak values. The device meets all AC/DC parameters in the presence of at least this much noise.

1 After this period, the first clock is generated.

2 The 9SQ44x device maintains 300ns data hold time for backwards compatibility with the SMBus 2.0 specification. Newer versions of the SMBus

specification call out 0ns data hold time for both 100kHz and 400kHz classes.

3 The 9SQ44x provided additional SMBus protection by implementing a timeout for SMBDATA being held low in excess of tTIMEOUT, in addition to the

SMBCLK low timeout.

4 Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of

tTIMEOUT, Minimum. After the master in a transaction detects this condition, it must generate a stop condition within or after the current data byte

in the transfer process. Devices that have detected this condition must reset their communication and be able to receive a new START condition

no later than tTIMEOUT, Maximum. Typical device examples include the host controller, and embedded controller, and most devices that can master

the SMBus. Some simple devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port

after a start or a stop condition. A timeout condition can only be ensured if the device that is forcing the timeout holds the SMBCLK low for tTIMEOUT,

Maximum or longer.

Table 12. Power Supply Noise Profile

Parameter

Symbol

Conditions

Minimum Typical Maximum

Units

Notes

Power Supply Noise

VDD_AC Single tone AC noise, swept.

—

50

—

mV

1

VDDA_AC VDD electrical noise > 20MHz.

—

50

—

mV

1

VDDXTAL VDD electrical noise 12kHz to 25MHz.

—

50

—

mV

1

Table 13. SMBus

Parameter

Symbol

100kHz Class Operation 400kHz Class Operation

Units Notes

Minimum

Maximum

Minimum

Maximum

SMBus Operating Frequency

fSMB

10

100

10

400

kHz

Bus Free Time between STOP and START Condition

tBUF

4.7

—

1.3

—

μs

Hold Time after (REPEATED) START Condition

tHD:STA

4

—

0.6

—

μs

1

REPEATED START Condition Setup Time

tSU:STA

4.7

—

0.6

—

μs

STOP Condition Setup Time

tSU:STO

4

—

0.6

—

μs

Data Hold Time

tHD:DAT

300

—

0

—

ns

2

Data Setup Time

tSU:DAT

250

—

100

—

ns

Detect SMBDAT Low Timeout

tTIMEOUT

25

35

25

35

ms

3

Detect Clock Low Timeout

tTIMEOUT

25

35

25

35

ms

4

Clock Low Period

tLOW

4.7

—

1.3

—

μs

Clock High Period

tHIGH

4

50

0.6

50

μs

5

Clock/Data Fall Time

tF

—

300

—

300

ns

6

Clock/Data Rise Time

tR

—

1000

—

300

ns

6

Time in which a device must be operational after power-on

reset

tPOR

—

500

—

500

ms

7