M40Z300 datasheet(2/16 Pages) STMICROELECTRONICS

2 / 16 page

M40Z300, M40Z300W

2/16

When an invalid VCC condition occurs, the condi-

tioned chip enable outputs (E1CON to E4CON ) are

forced inactive to write-protect the stored data in

the SRAM. During a power failure, the SRAM is

switched from the VCC pin to the lithium cell within

the SNAPHAT to provide the energy required for

data retention. On a subsequent power-up, the

SRAM remains write protected until a valid power

condition returns.

The 28 pin, 330 mil SOIC provides sockets with

gold plated contacts for direct connection to a sep-

arate SNAPHAT housing containing the battery.

The SNAPHAT housing has gold plated pins

which mate with the sockets, ensuring reliable

connection. The housing is keyed to prevent im-

proper insertion. This unique design allows the

SNAPHAT battery package to be mounted on top

of the SOIC package after the completion of the

surface mount process which greatly reduces the

board manufacturing process complexity of either

directly soldering or inserting a battery into a sol-

dered holder. Providing non-volatility becomes a

"SNAP".

The 16 pin SOIC provides battery pins for an ex-

ternal user supplied battery.

Figure 2A. SOIC28 Connections

AI02243

RST

E1CON

E3CON

E2CON

THS

VSS

E4CON

VOUT

VCC

M40Z300

M40Z300W

Table 1. Signal Names

THS

Threshold Select Input

Chip Enable Input

E1CON-E4CON

Conditioned Chip Enable Output

A, B

Decoder Inputs

RST

Reset Output (Open Drain)

Battery Low Output (Open Drain)

VOUT

Supply Voltage Output

VCC

Supply Voltage

VSS

Ground

B+

Positive Battery Pin

B–

Negative Battery Pin

Not Connected Internally

Figure 2B. SOIC16 Connections

AI03624

710

RST

E1CON

E2CON

B– (B+)

VSS

VOUT

VCC

M40Z300

M40Z300W

THS

E3CON

E4CON

B+ (B–)

( ) = M40Z300W

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