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9FGL02X1 Datasheet(PDF) 13 Page - Renesas Technology Corp

Part # 9FGL02X1
Description  3.3V PCIe Gen1-6 Clock Generator Family
PDF  37 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

9FGL02X1 Datasheet(HTML) 13 Page - Renesas Technology Corp

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R31DS0112EU0107 Rev.1.07
Page 13
Dec 13, 2024
9FGL02x1/04x1/06x1/08x1D Datasheet
Avg. Clock Period Accuracy
TPERIOD_AVG
9FGL0xxx devices have 0 ppm
synthesis error. -0.5% SSC. [1][7][8][9]
-
0
+2500
ppm
-0.25% SSC
-
0
+1250
Absolute Period
TPERIOD_ABS
Includes jitter and spread spectrum
modulation. [1][10]
9.95
10
10.0503
ns
Jitter, Cycle to Cycle [1]
tjcyc-cyc
-
16
50
ps
Voltage High [3]
VHIGH
Statistical measurement on single-
ended signal using oscilloscope math
function (scope averaging on).
660
790
850
mV
Voltage Low [3]
VLOW
-150
-4
150
mV
Absolute Maximum Voltage
[3][11][12]
VMIN
Measurement on single-ended signal
using absolute value (scope averaging
off).
-
832
1150
mV
Absolute Minimum Voltage
[3][12][13]
VMAX
-300
-61
-
mV
Duty Cycle [1]
tDC
45
48.6
55
%
Slew Rate Matching [3][14]
ΔTrf
Single-ended measurement.
-
9
20
%
Skew, Output to Output [1]
tsk3
Averaging on, VT = 50%.
-
32
50
ps
1. Measured from differential waveform.
2. Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be
monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero
crossing.
3. Measured from single-ended waveform.
4. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
6. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance
in VCROSS for any particular system.
7. Refer to Section 8.6.2 of the PCI Express Base Specification, Revision 5.0 for information regarding PPM considerations.
8. PCIe Gen1 through Gen4 specify ±300ppm frequency tolerances. PCIe Gen5 reduces the allowable tolerance to ±100ppm without
spread spectrum.
9. “ppm” refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of 100.000000MHz exactly
or 100Hz. For 100ppm, then we have an error budget of 100Hz/ppm × 100ppm = 10kHz. The period is to be measured with a frequency
counter with measurement window set to 100ms or greater. The ±100ppm applies to systems that do not employ Spread Spectrum
clocking, or that use common clock source. For systems employing Spread Spectrum clocking, there is an additional 2,500ppm nominal
shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,600ppm for
Common Clock architectures. Separate Reference Clock architectures may have a lower allowed spread percentage.
10. Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative ppm tolerance, and spread
spectrum modulation.
11. Defined as the maximum instantaneous voltage including overshoot.
12. At default SMBus amplitude settings.
13. Defined as the minimum instantaneous voltage including undershoot.
14. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on
the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of
REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate.
15. System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors
CL. Single-ended probes must be used for measurements requiring single ended measurements. Either single-ended probes with math
or differential probe can be used for differential measurements. Test load CL = 2pF.
Table 7. Differential Low-Power HCSL Outputs (Cont.)
Parameter
Symbol
Conditions
Minimum Typical Maximum
Unit



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