COP8TAB9 datasheet(21/59 Pages) NSC

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10.0 Functional Description

(Continued)

10.8 CONTROL REGISTERS

10.8.1 CNTRL Register (Address X'00EE)

T1C3

T1C2

T1C1

T1C0

MSEL

IEDG

SL1

SL0

Bit 7

Bit 0

The Timer1 (T1) and MICROWIRE/PLUS control register

contains the following bits:

T1C3

Timer T1 mode control bit

T1C2

Timer T1 mode control bit

T1C1

Timer T1 mode control bit

T1C0

Timer

Start/Stop

control

timer

modes 1 and

Underflow

Interrupt

Pending Flag in timer mode 3

MSEL

Selects G5 and G4 as MICROWIRE/PLUS

signals SK and SO respectively

IEDG

External

interrupt

edge

polarity

select

(0 = Rising edge, 1 = Falling edge)

SL1 & SL0 Select the MICROWIRE/PLUS clock divide

by (00 = 2, 01 = 4, 1x = 8)

10.8.2 PSW Register (Address X'00EF)

T1PNDA

T1ENA

EXPND

BUSY

EXEN

GIE

Bit 7

Bit 0

The PSW register contains the following select bits:

Half Carry Flag

Carry Flag

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA

in mode 1, T1 Underflow in Mode 2, T1A capture

edge in mode 3)

T1ENA

Timer T1 Interrupt Enable for Timer Underflow

or T1A Input capture edge

EXPND

External interrupt pending

BUSY

MICROWIRE/PLUS busy shifting flag

EXEN

Enable external interrupt

GIE

Global interrupt enable (enables interrupts)

The Half-Carry flag is also affected by all the instructions that

affect the Carry flag. The SC (Set Carry) and RC (Reset

Carry) instructions will respectively set or clear both the carry

flags. In addition to the SC and RC instructions, ADC, SUBC,

RRC and RLC instructions affect the Carry and Half Carry

flags.

10.8.3 ICNTRL Register (Address X'00E8)

Unused

LPEN

T0PND

T0EN

µWPND

µWEN

T1PNDB

T1ENB

Bit 7

Bit 0

The ICNTRL register contains the following bits:

LPEN

L/C

Port

Interrupt

Enable

(Multi-Input

Wake-Up/Interrupt)

T0PND

Timer T0 Interrupt pending

T0EN

Timer T0 Interrupt Enable (Bit 12 toggle)

µWPND MICROWIRE/PLUS interrupt pending

µWEN

Enable MICROWIRE/PLUS interrupt

T1PNDB Timer T1 Interrupt Pending Flag for T1B capture

edge

T1ENB

Timer T1 Interrupt Enable for T1B Input capture

edge

10.8.4 ITMR Register (Address X'00CF)

RSVD

ITSEL2

ITSEL1

ITSEL0

Bit 7

Bit 0

The ITMR register contains the following bits:

RSVD

These bits are reserved and must be 0.

ITSEL2 Idle Timer period select bit.

ITSEL1 Idle Timer period select bit.

ITSEL0 Idle Timer period select bit.

11.0 In-System Programming

11.1 INTRODUCTION

This device provides the capability to program the program

memory while installed in an application board. This feature

is called In System Programming (ISP). It provides a means

of ISP by using the MICROWIRE/PLUS, or the user can

provide his own, customized ISP routine. The factory in-

stalled ISP uses the MICROWIRE/PLUS port. The user can

provide his own ISP routine that uses any of the capabilities

of the device, such as ACCESS.Bus, parallel port, etc. The

user is cautioned, however, to remove all calls to Boot ROM

functions prior to submission of code for ROM generation

and production in COP8TAx5 devices.

11.2 FUNCTIONAL DESCRIPTION

The organization of the ISP feature consists of the user

Flash program memory, the factory boot ROM, and some

registers dedicated to performing the ISP function. See Fig-

ure 18 for a simplified block diagram. The factory installed

ISP that uses MICROWIRE/PLUS is located in the Boot

ROM. The size of the Boot ROM is 1k bytes and also

contains code to facilitate in system emulation capability. If a

user chooses to write an application specific ISP routine, it

must be located in the Flash program memory.

As described in Section 10.4 OPTION REGISTER, there is a

bit, FLEX, that controls whether the device exits RESET

executing from the Flash memory or the Boot ROM. The

user must program the FLEX bit as appropriate for the

application. In the erased state, the FLEX bit = 0 and the

device will power-up executing from Boot ROM. When FLEX

= 0, this assumes that either the MICROWIRE/PLUS ISP

20047529

FIGURE 18. Block Diagram of ISP

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