ST72361 datasheet(158/224 Pages) STMICROELECTRONICS

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ST72361

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LINSCI

™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)

10.8.4.7 Parity control

Parity control (generation of parity bit in transmis-

sion and parity checking in reception) can be ena-

bled by setting the PCE bit in the SCICR1 register.

Depending on the frame length defined by the M

bit, the possible SCI frame formats are as listed in

Table 24.

Table 25. Frame Formats

Legend:

SB: Start Bit

STB: Stop Bit

PB: Parity Bit

Note: In case of wake up by an address mark, the

MSB bit of the data is taken into account and not

the parity bit

Even parity: The parity bit is calculated to obtain

an even number of “1s” inside the frame made of

the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit

is 0 if even parity is selected (PS bit = 0).

Odd parity: The parity bit is calculated to obtain

an odd number of “1s” inside the frame made of

the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit

is 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the

MSB bit of the data written in the data register is

not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the in-

terface checks if the received data byte has an

even number of “1s” if even parity is selected

(PS = 0) or an odd number of “1s” if odd parity is

selected (PS = 1). If the parity check fails, the PE

flag is set in the SCISR register and an interrupt is

generated if PIE is set in the SCICR1 register.

10.8.5 Low Power Modes

10.8.6 Interrupts

The SCI interrupt events are connected to the

same interrupt vector.

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the inter-

rupt mask in the CC register is reset (RIM instruc-

tion).

M bit

PCE bit

SCI frame

| SB | 8 bit data | STB |

| SB | 7-bit data | PB | STB |

| SB | 9-bit data | STB |

| SB | 8-bit data PB | STB |

Mode

Description

WAIT

No effect on SCI.

SCI interrupts cause the device to exit from

Wait mode.

HALT

SCI registers are frozen.

In Halt mode, the SCI stops transmitting/re-

ceiving until Halt mode is exited.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Transmit Data Register

Empty

TDRE

TIE

Yes

Transmission Com-

plete

TCIE

Received Data Ready

to be Read

RDRF

RIE

Overrun Error Detect-

Idle Line Detected

IDLE

ILIE

Parity Error

PIE

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