R3119x-Y

NO.EA-378-160613

13

POWER SEQUENCE

The R3119xxxxE can supervise the voltage of the SENSE pin. Regarding the power-on sequence, the SENSE

pin must be powered on after the power-on to the VDD pin, as shown below.

If the SENSE pin voltage is equal or more than the released voltage (+VDET), DOUT pin becomes "H". Besides,

a voltage beyond VDD pin is also acceptable to SENSE pin.

t

VDD

VDOUT

VSENSE

+VDET

Power-On Timing Diagram

GLITCH DETECTION by VDD, SENSE PINS

The following graphs are the released conditions when a pulse voltage less than or equal to the detector

threshold (−VDET) is applied to VDD (R3119xxxxA) / VSENSE (R3119xxxxE) pin during the release operation. This

graph indicates the maximum pulse condition. If a pulse increased in width and voltage is applied to VDD

(R3119xxxxA) / VSENSE (R3119xxxxE), the reset signal may occur.

R3119xxxxA Pulse Width vs. Over Drive Voltage R3119xxxxE Pulse Width vs. Over Drive Voltage

−VDET

Over Drive

Pulse Width

VDD / VSENSE

VDD / VSENSE Input Waveform

0

50

100

150

200

250

300

350

1

10

100

1000

Over Drive Voltage (mV)

R3119x120A

R3119x023A

0

50

100

150

200

250

300

350

1

10

100

1000

Over Drive Voltage (mV)

R3119x120E

R3119x023E