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LMKDB1120FS85NPPR Datasheet(PDF) 21 Page - Texas Instruments

Part # LMKDB1120FS85NPPR
Description  LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family
PDF  133 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

LMKDB1120FS85NPPR Datasheet(HTML) 21 Page - Texas Instruments

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Table 5-6. LMKDB1102 Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME(2) (3)
NO.
^OE2#
12
I
Active low input to control CLK2. Internal pullup resistor.
0 = Output Active, 1 = Output Inactive
LOS#
13
O
Loss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup
resistor.
Low = Invalid input clock.
High = Valid input clock.
vZOUT_SEL
11
I
LP-HCSL differential clock output impedance select. Internal pulldown resistor.
Low = 85Ω.
High = 100Ω.
NC
4, 5
NC
No connect.
(1)
I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2)
Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an
internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating.
(3)
The "#" symbol indicates active low.
www.ti.com
LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS
LMKDB1112, LMKDB1120, LMKDB1120FS
SNAS855G – NOVEMBER 2023 – REVISED MAY 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS



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