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TMS320DM647_0804 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM647_0804 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 182 page  1 TMS320DM647/TMS320DM648 Digital Media Processor 1.1 Features TMS320DM647/TMS320DM648 Digital Media Processor www.ti.com SPRS372B – MAY 2007 – REVISED APRIL 2008 • High-Performance Digital Media Processor • C64x+ L1/L2 Memory Architecture (DM647/DM648) – 256K-bit (32K-byte) L1P Program – 720, 900-MHz C64x+™ Clock Rate RAM/Cache [Direct Mapped] – 1.39, 1.11-ns Instruction Cycle Time – 256K-bit (32K-byte) L1D Data RAM/Cache [2-Way Set-Associative] – 5760, 7200 MIPS – 2M-bit/256K-byte (DM647) or – Eight 32-Bit C64x+ Instructions/Cycle 4M-Bit/512K-byte) (DM648) L2 Unified – Fully Software-Compatible With Mapped RAM/Cache [Flexible Allocation] C64x/Debug • Supports Little Endian Mode Only – Commercial Temperature Ranges • Five Configurable Video Ports • VelociTI.2™ Extensions to VelociTI™ – Providing a Glueless I/F to Common Video Advanced Very-Long-Instruction-Word (VLIW) Decoder and Encoder Devices TMS320C64x+™ DSP Core – Supports Multiple Resolutions/Video – Eight Highly Independent Functional Units Standards With VelociTI.2 Extensions: • VCXO Interpolated Control Port (VIC) • Six ALUs (32-/40-Bit), Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit – Supports Audio/Video Synchronization Arithmetic per Clock Cycle • External Memory Interfaces (EMIFs) • Two Multipliers Support Four 16 x 16-bit – 32-Bit DDR2 SDRAM Memory Controller Multiplies (32-bit Results) per Clock With 512M-Byte(1) Address Space (1.8-V I/O) Cycle or Eight 8 x 8-bit Multiplies (16-Bit – Asynchronous 16-Bit Wide EMIF (EMIFA) Results) per Clock Cycle • Up to 128M-Byte Total Address Reach – Load-Store Architecture With Non-Aligned • 64M-Byte Address Reach per CE Space Support – Glueless Interface to Asynchronous – 64 32-bit General-Purpose Registers Memories (SRAM, Flash, and EEPROM) – Instruction Packing Reduces Code Size – Synchronous Memories (SBSRAM and ZBT – All Instructions Conditional SRAM) – Additional C64x+™ Enhancements – Supports Interface to Standard Sync • Protected Mode Operation Devices and Custom Logic (FPGA, CPLD, • Exceptions Support for Error Detection ASICs, etc.) and Program Redirection • Enhanced Direct-Memory-Access (EDMA) • Hardware Support for Modulo Loop Controller (64 Independent Channels) Auto-Focus Module Operation • 3-Port Gigabit Ethernet Switch Subsystem • C64x+ Instruction Set Features • Four 64-Bit General-Purpose Timers (Each – Byte-Addressable (8-/16-/32-/64-bit Data) Configurable as Two 32-Bit Timers) – 8-bit Overflow Protection • One UART (With RTS and CTS Flow Control) – Bit-Field Extract, Set, Clear • One 4-wire Serial Port Interface (SPI) With Two – Normalization, Saturation, Bit-Counting Chip-Selects – VelociTI.2 Increased Orthogonality • Master/Slave Inter-Integrated Circuit (I2C – C64x+ Extensions Bus™) • Compact 16-bit Instructions • Additional Instructions to Support • Multichannel Audio Serial Port (McASP) Complex Multiplies – Ten Serializers and SPDIF (DIT) Mode • 16/32-Bit Host-Port Interface (HPI) • Advanced Event Triggering (AET) Compatible (1) From Silicon revision 1.1 and onward. In silicon revision 1.0, the address space in bytes are 256M. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PRODUCTION DATA information is current as of publication date. Copyright © 2007–2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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