M58BW016DB datasheet(13/63 Pages) STMICROELECTRONICS

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M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A18). The Address Inputs

are used to select the cells to access in the mem-

ory array during Bus Read operations either to

read or to program data to. During Bus Write oper-

ations they control the commands sent to the

Command Interface of the internal state machine.

Chip Enable must be low when selecting the ad-

dresses.

The address inputs are latched on the rising edge

of Latch Enable L or Burst Clock K, whichever oc-

curs first, in a read operation.The address inputs

are latched on the rising edge of Chip Enable,

Write Enable or Latch Enable, whichever occurs

first in a Write operation. The address latch is

transparent when Latch Enable is low, VIL. The ad-

dress is internally latched in an Erase or Program

operation.

Data Inputs/Outputs (DQ0-DQ31). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation, or are used

to input the data during a program operation. Dur-

ing Bus Write operations they represent the com-

mands sent to the Command Interface of the

internal state machine. When used to input data or

Write commands they are latched on the rising

edge of Write Enable or Chip Enable, whichever

occurs first.

When Chip Enable and Output Enable are both

low, VIL, and Output Disable is at VIH, the data bus

outputs data from the memory array, the Electron-

ic Signature, the CFI Information or the contents of

the Status Register. The data bus is high imped-

ance when the device is deselected with Chip En-

able at VIH, Output Enable at VIH, Output Disable

at VIL or Reset/Power-Down at VIL. The Status

DQ31 are at VIL.

Chip Enable (E). The Chip Enable, E, input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. Chip Enable, E, at

VIH deselects the memory and reduces the power

consumption to the Standby level.

Output Enable (G). The Output Enable, G, gates

the outputs through the data output buffers during

a read operation, when Output Disable GD is at

VIH. When Output Enable G is at VIH, the outputs

are high impedance independently of Output Dis-

able.

Output Disable (GD). The Output Disable, GD,

deactivates the data output buffers. When Output

Disable, GD, is at VIH, the outputs are driven by

the Output Enable. When Output Disable, GD, is at

VIL, the outputs are high impedance independent-

ly of Output Enable. The Output Disable pin must

be connected to an external pull-up resistor as

there is no internal pull-up resistor to drive the pin.

Write Enable (W). The Write Enable, W, input

controls writing to the Command Interface, Input

Address and Data latches. Both addresses and

data can be latched on the rising edge of Write En-

able (also see Latch Enable, L).

Reset/Power-Down (RP). The

Reset/Power-

Down, RP, is used to apply a hardware reset to the

memory. A hardware reset is achieved by holding

Reset/Power-Down Low, VIL, for at least tPLPH.

Writing is inhibited to protect data, the Command

Interface and the Program/Erase Controller are re-

set. The Status Register information is cleared and

power consumption is reduced to deep power-

down level. The device acts as deselected, that is

the data outputs are high impedance.

After Reset/Power-Down goes High, VIH, the

memory will be ready for Bus Read operations af-

ter a delay of tPHEL or Bus Write operations after

tPHWL.

If Reset/Power-Down goes low, VIL, during a Block

Erase, a Program or a Tuning Protection Program

the operation is aborted, in a time of tPLRH maxi-

mum, and data is altered and may be corrupted.

During Power-up power should be applied simulta-

neously to VDD and VDDQ(IN) with RP held at VIL.

When the supplies are stable RP is taken to VIH.

Output Enable, G, Chip Enable, E, and Write En-

able, W, should be held at VIH during power-up.

In an application, it is recommended to associate

Reset/Power-Down pin, RP, with the reset signal

of the microprocessor. Otherwise, if a reset opera-

tion occurs while the memory is performing an

erase or program operation, the memory may out-

put the Status Register information instead of be-

ing

initialized

the

default

Asynchronous

Random Read.

See Table 21 and Figure 18, Reset, Power-Down

and Power-up Characteristics, for more details.

Latch Enable (L). The Bus Interface can be con-

figured to latch the Address Inputs on the rising

edge of Latch Enable, L, for Asynchronous Latch

Enable Controlled Read or Write or Synchronous

Burst Read operations. In Synchronous Burst

Read operations the address is latched on the ac-

tive edge of the Clock when Latch Enable is Low,

VIL. Once latched, the addresses may change

without affecting the address used by the memory.

When Latch Enable is Low, VIL, the latch is trans-

parent. Latch Enable, L, can remain at VIL for

Asynchronous Random Read and Write opera-

tions.

Burst Clock (K). The Burst Clock, K, is used to

synchronize the memory with the external bus dur-

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