M68AW064F datasheet(11/18 Pages) STMICROELECTRONICS

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M68AW064F

Write Mode

The M68AW064F is in the Write mode whenever

the W and E are Low. Either the Chip Enable input

(E) or the Write Enable input (W) must be de-

asserted

during

Address

transitions

for

subsequent write cycles. When E (W) is Low, and

UB or LB is Low, write cycle begins on the W (E)’s

falling edge. Therefore, address setup time is

referenced to Write Enable as tAVWL and to Chip

Enable as tAVEL and is determined by the latter

occurring edge.

The Write cycle can be terminated by the earlier

rising edge of E or W.

If the Output is enabled (E = Low, G = Low, LB or

UB = Low), then W will return the outputs to high

impedance within tWLQZ of its falling edge. Care

must be taken to avoid bus contention in this type

of operation. Data input must be valid for tDVWH

before the rising edge of Write Enable, or for tDVEH

before the rising edge of E, whichever occurs first,

and remain valid for tWHDX and tEHDX respectively.

Figure 10. Write Enable Controlled, Write AC Waveforms

AI04878

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A15

DQ0-DQ15

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

tBLWH

UB, LB

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