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M58LW064 Datasheet(PDF) 16 Page - STMicroelectronics |
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M58LW064 Datasheet(HTML) 16 Page - STMicroelectronics |
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16 / 53 page ![]() M58LW064A, M58LW064B 16/53 Table 10. Burst Configuration Register (1) Note: 1. The BCR defines both the read mode and the burst configuration. 2. Synchronous burst length is defined as Word or Double-Word, the data bus width depends only on the WORD input. Asynchronous Page read is two Words or one Double-Word. 3. A burst length of 8 is not available for x32 organisation. 4. At FK > 50MHz when X-Latency = 10 or 12, Y-Latency = 2 independent of the value of M9. At FK = 66MHz when X-Lantency = 14 or 16, Y-Latency = 2 indepedent of the value of M9. 5. Latency 7 valid only for continuous burst. Otherwisw Latency = 8. 6. Latency 10 valid only for continuous burst. Otherwisw Latency = 12. 7. Latency 11 valid only for continuous burst. Otherwisw Latency = 12. 8. Latency 14 valid only for continuous burst. Otherwisw Latency = 16. BCR mode bit Description Value Description M15 Read Select 0 Synchronous Burst Read 1 Asynchronous Read M14-M11 X-Latency (4) 0001 Reserved 0010 7, only for FK = 33MHz (5) 0011 8, only for FK = 33MHz 0100 9, only for FK = 33MHz 0101 10, only for FK = 50MHz (6) 0110 11, only for FK = 50MHz (7) 1001 12, only for FK = 50MHz 1010 13, only for FK = 50MHz 1011 14, only for FK = 66MHz (8) 1101 16, only for FK = 66MHz M9 Y-Latency (4) 0 One Burst Clock cycle 1 Two Burst Clock cycles M8 Valid Data Ready 0 R valid Low during valid Burst Clock edge 1 R valid Low one data cycle before valid Burst Clock edge M7 Burst Type 0 Interleaved 1 Sequential M6 Valid Clock Edge 0 Falling Burst Clock edge 1 Rising Burst Clock edge M3 Asynchronous 0 Random Read 1 Latch Enable Controlled Read M2-M0 Burst Length (2) 100 1 Word or Double-Word 101 2 Words or Double-Words 001 4 Words or Double-Words 010 8 Words or Double-Words (3) 111 Continuous |
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