EM78F651NAM datasheet(36/58 Pages) EMC

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EM78F651N

8-Bit Microcontroller

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Product Specification (V1.1) 10.20.2006

(This specification is subject to change without further notice)

When Vdd drops below VLVD, LVDIF is set to “1”. If global ENI enable, LVDIF will be

set to “1”, the next instruction will branch to interrupt vector. The LVD interrupt flag is

cleared to “0” by software.

When Vdd drops below VRESET and is less than 80µs, the system will all maintain the

VRESET and is more than 80µs, a system reset will occur, and for the following

waveform situation, refer to Section 6.5.1 Reset Description.

Vdd

LVDXIF

Internal Reset

VLVD

VRESET

LVDXIF clear by software

Vdd < Vreset not longer than 80us,system keep on going

>50,40,30 us

<50,40,30 us

18ms

System occur reset

Fig. 6-9 LVD Waveform Situation

6.8 Data EEPROM

The Data EEPROM is readable and writable during normal operation over the whole

Vdd range. The operation for Data EEPROM is base on a single byte. A write

operation makes an erase-then-write cycle to take place on the allocated byte.

The Data EEPROM memory provides high erase and write cycles. A byte write

automatically erases the location and writes the new value.

6.8.1 Data EEPROM Control Register

6.8.1.1 RB (EEPROM Control Register)

The EECR (EEPROM Control Register) is the control register for configuring and

initiating the control register status.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EEWE

EEDF

EEPC

Bit 7

：Read control register

0 : Does not execute EEPROM read

1 : Read EEPROM content, (RD can be set by software, RD is cleared by

hardware after Read instruction is completed)

Bit 6

：Write control register

0 : Write cycle to the EEPROM is complete.

1 : Initiate a write cycle, (WR can be set by software, WR is cleared by

hardware after Write cycle is completed)

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