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AS7038RB Datasheet(PDF) 101 Page - ams-OSRAM AG |
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AS7038RB Datasheet(HTML) 101 Page - ams-OSRAM AG |
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101 / 127 page ![]() Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 100 ADC_CFGB (Address 0x89) Figure 133: ADC_CFGB Register Addr: 0x89 ADC_CFGB Bit Bit Name Default Access Bit Description 7:6 Not used 0 RW Not used 5:3 adc_clock 0 RW ADC clock divider: The ADC clock is freely configurable Setting Periods µs kHz 0 2 1 1000 1 4 2 500 2 6 3 333 3 8 4 250 4 10 5 200 5 12 6 167 6 14 7 143 7 16 8 125 2 adc_calibration 0 RW To activate the optional self calibration, this bit must be asserted, and an ADC “conversion” has to be started in manual mode (man_mode=1) by asserting seq_start. 1 ulp 0 RW Ultra low power bit for the sequencer. If this bit is set and sd_subs>0, it disables the LED pulses and powers off the TIA in all sequences but the one where the TIA is sampled. 0 adc_en 0 RW 0: Reset ADC 1: Enable ADC Warning: In reset state the ADC clears its calibration data. Re-calibration is necessary next time it is enabled again. ADC_CFGC (Address 0x8a) Figure 134: ADC_CFGC Register Addr: 0x8a ADC_CFGC Bit Bit Name Default Access Bit Description 7:5 Not used 0 RW Not used |
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